mb/google/brya/var/orisa: Update Type C DisplayPort HPD Configuration
[coreboot2.git] / src / mainboard / google / brya / variants / crota / gpio.c
blobbe9b74cae3f27d0059dc2fb221e08c6259a0b66e
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <commonlib/helpers.h>
6 #include <soc/gpio.h>
8 /* Pad configuration in ramstage */
9 static const struct pad_config override_gpio_table[] = {
10 /* A6 : ESPI_ALERT1# ==> NC */
11 PAD_NC(GPP_A6, NONE),
12 /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
13 PAD_CFG_GPO(GPP_A12, 1, DEEP),
14 /* A19 : DDSP_HPD1 ==> WWAN_FCPO_L */
15 PAD_CFG_GPO(GPP_A19, 1, DEEP),
16 /* A20 : DDSP_HPD2 ==> WWAN_RST_L */
17 PAD_CFG_GPO(GPP_A20, 1, DEEP),
18 /* A21 : DDPC_CTRCLK ==> NC */
19 PAD_NC(GPP_A21, NONE),
20 /* A22 : DDPC_CTRLDATA ==> NC */
21 PAD_NC(GPP_A22, NONE),
22 /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
23 PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
25 /* B2 : VRALERT# ==> BYPASS_DET */
26 PAD_CFG_GPI(GPP_B2, NONE, DEEP),
27 /* B3 : PROC_GP2 ==> NC */
28 PAD_NC(GPP_B3, NONE),
29 /* B15 : PROC_GP3 ==> AUD_RST_L */
30 PAD_CFG_GPO(GPP_B15, 1, PWROK),
32 /* C3 : GPP_C3 ==> SML0_SMBCLK */
33 PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
34 /* C4 : GPP_C4 ==> SML0_SMBDATA */
35 PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
37 /* D3 : ISH_GP3 ==> NC */
38 PAD_NC(GPP_D3, NONE),
39 /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
40 PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
41 /* D13 : ISH_UART0_RXD ==> NC */
42 PAD_NC(GPP_D13, NONE),
43 /* D14 : ISH_UART0_TXD ==> NC */
44 PAD_NC(GPP_D14, NONE),
45 /* D15 : ISH_UART0_RTS# ==> NC */
46 PAD_NC(GPP_D15, NONE),
47 /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
48 PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
49 /* D19 : I2S_MCLK1_OUT ==> NC */
50 PAD_NC(GPP_D19, NONE),
52 /* E3 : PROC_GP0 ==> NC */
53 PAD_NC(GPP_E3, NONE),
54 /* E5 : SATA_DEVSLP1 ==> NC */
55 PAD_NC(GPP_E5, NONE),
56 /* E7 : PROC_GP1 ==> NC */
57 PAD_NC(GPP_E7, NONE),
58 /* E20 : DDP2_CTRLCLK ==> NC */
59 PAD_NC(GPP_E20, NONE),
60 /* E21 : DDP2_CTRLDATA ==> NC */
61 PAD_NC(GPP_E21, NONE),
62 /* E22 : DDPA_CTRLCLK ==> NC */
63 PAD_NC(GPP_E22, NONE),
64 /* E23 : DDPA_CTRLDATA ==> NC */
65 PAD_NC(GPP_E23, NONE),
67 /* F19 : SRCCLKREQ6# ==> FP_USER_PRES_FP_L */
68 PAD_CFG_GPI(GPP_F19, NONE, DEEP),
69 /* F20 : EXT_PWR_GATE# ==> NC */
70 PAD_NC(GPP_F20, NONE),
72 /* H21 : IMGCLKOUT2 ==> VPRO_STRAP */
73 PAD_CFG_GPI(GPP_H21, NONE, DEEP),
74 /* H22 : IMGCLKOUT3 ==> NC */
75 PAD_NC(GPP_H22, NONE),
77 /* R4 : HDA_RST# ==> DMIC_CLK0_R */
78 PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
79 /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
80 PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
81 /* R6 : I2S2_TXD ==> NC */
82 PAD_NC(GPP_R6, NONE),
83 /* R7 : I2S2_RXD ==> NC */
84 PAD_NC(GPP_R7, NONE),
86 /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */
87 PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
88 /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */
89 PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
90 /* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */
91 PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
92 /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */
93 PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
94 /* S4 : SNDW2_CLK ==> NC */
95 PAD_NC(GPP_S4, NONE),
96 /* S5 : SNDW2_DATA ==> NC */
97 PAD_NC(GPP_S5, NONE),
98 /* S6 : SNDW3_CLK ==> NC */
99 PAD_NC(GPP_S6, NONE),
100 /* S7 : SNDW3_DATA ==> NC */
101 PAD_NC(GPP_S7, NONE),
103 /* T2 : GPP_T2 ==> eMMC_CFG */
104 PAD_CFG_GPI(GPP_T2, NONE, DEEP),
106 /* GPD11: LANPHYC ==> NC */
107 PAD_NC(GPD11, NONE),
108 PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
109 PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
110 PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
111 PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
112 PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
113 PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
114 PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
115 PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
118 /* Early pad configuration in bootblock */
119 static const struct pad_config early_gpio_table[] = {
120 /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
121 PAD_CFG_GPO(GPP_A12, 1, DEEP),
122 /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
123 PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
124 /* A19 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
125 PAD_CFG_GPO(GPP_A19, 0, DEEP),
126 /* A20 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
127 PAD_CFG_GPO(GPP_A20, 0, DEEP),
128 /* B3 : PROC_GP2 ==> eMMC_PERST_L */
129 PAD_CFG_GPO(GPP_B3, 0, DEEP),
130 /* B4 : PROC_GP3 ==> SSD_PERST_L */
131 PAD_CFG_GPO(GPP_B4, 0, DEEP),
132 /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
133 PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
134 /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
135 PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
137 * D1 : ISH_GP1 ==> FP_RST_ODL
138 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
139 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
140 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
141 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
142 * FPMCU not working after a S3 resume. This is a known issue.
144 PAD_CFG_GPO(GPP_D1, 0, DEEP),
145 /* D2 : ISH_GP2 ==> EN_FP_PWR */
146 PAD_CFG_GPO(GPP_D2, 1, DEEP),
147 /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
148 PAD_CFG_GPO(GPP_D11, 1, DEEP),
149 /* D18 : UART1_TXD ==> SD_PE_RST_L */
150 PAD_CFG_GPO(GPP_D18, 0, PLTRST),
151 /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
152 PAD_CFG_GPO(GPP_E0, 0, DEEP),
153 /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
154 PAD_CFG_GPI(GPP_E13, NONE, DEEP),
155 /* E15 : RSVD_TP ==> PCH_WP_OD */
156 PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
157 /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
158 PAD_CFG_GPI(GPP_F18, NONE, DEEP),
160 /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
161 PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
162 /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
163 PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
164 /* H13 : I2C7_SCL ==> EN_PP3300_SD */
165 PAD_CFG_GPO(GPP_H13, 1, PLTRST),
167 /* CPU PCIe VGPIO for PEG60 */
168 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
169 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
170 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
171 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
172 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
173 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
174 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
175 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
176 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
177 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
178 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
179 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
180 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
181 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
182 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
183 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
184 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
185 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
186 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
187 PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
190 static const struct pad_config romstage_gpio_table[] = {
191 /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
192 PAD_CFG_GPO(GPP_A12, 1, DEEP),
193 /* B4 : PROC_GP3 ==> SSD_PERST_L */
194 PAD_CFG_GPO(GPP_B4, 1, DEEP),
195 /* A19 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
196 PAD_CFG_GPO(GPP_A19, 1, DEEP),
197 /* A20 : EXT_PWR_GATE2# ==> WWAN_RST_L (set here for correct power sequencing) */
198 PAD_CFG_GPO(GPP_A20, 0, DEEP),
200 /* Enable touchscreen, hold in reset */
201 /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
202 PAD_CFG_GPO(GPP_C0, 1, DEEP),
203 /* C1 : SMBDATA ==> USI_RST_L */
204 PAD_CFG_GPO(GPP_C1, 0, DEEP),
206 /* D1 : ISH_GP1 ==> FP_RST_ODL */
207 PAD_CFG_GPO(GPP_D1, 0, DEEP),
208 /* D2 : ISH_GP2 ==> EN_FP_PWR */
209 PAD_CFG_GPO(GPP_D2, 0, DEEP),
212 const struct pad_config *variant_gpio_override_table(size_t *num)
214 *num = ARRAY_SIZE(override_gpio_table);
215 return override_gpio_table;
218 const struct pad_config *variant_early_gpio_table(size_t *num)
220 *num = ARRAY_SIZE(early_gpio_table);
221 return early_gpio_table;
224 const struct pad_config *variant_romstage_gpio_table(size_t *num)
226 *num = ARRAY_SIZE(romstage_gpio_table);
227 return romstage_gpio_table;