src/mainboard/google/brya/variants/lisbon/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A14 : USB_OC1# ==> NC */
  11         PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG),
  12         /* A15 : USB_OC2# ==> NC */
  13         PAD_NC_LOCK(GPP_A15, NONE, LOCK_CONFIG),
  14         /* A18 : DDSP_HPDB ==> HDMIB_HPD */
  15         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  16         /* A19 : DDSP_HPD1 ==> NC */
  17         PAD_NC_LOCK(GPP_A19, NONE, LOCK_CONFIG),
  18         /* A20 : DDSP_HPD2 ==> NC */
  19         PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
  20         /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */
  21         PAD_CFG_GPO(GPP_A21, 1, DEEP),
  22         /* A22 : DDPC_CTRLDATA ==> NC */
  23         PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
  24
  25         /* B2  : VRALERT# ==> M2_SSD_PLA_L */
  26         PAD_NC(GPP_B2, NONE),
  27         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
  28         PAD_CFG_GPO(GPP_B3, 1, DEEP),
  29         /* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
  30         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  31         /* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
  32         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  33
  34         /* D0  : ISH_GP0 ==> NC */
  35         PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
  36         /* D1  : ISH_GP1 ==> NC */
  37         PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
  38         /* D2  : ISH_GP2 ==> NC */
  39         PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
  40         /* D3  : ISH_GP3 ==> NC */
  41         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  42         /* D9  : ISH_SPI_CS# ==> NC */
  43         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  44         /* D10 : ISH_SPI_CLK ==> GPI */
  45         PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG),
  46         /* D17 : UART1_RXD ==> NC */
  47         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  48
  49         /* E4  : SATA_DEVSLP0 ==> NC */
  50         PAD_NC(GPP_E4, NONE),
  51         /* E5  : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
  52         PAD_CFG_GPO(GPP_E5, 1, DEEP),
  53         /* E14 : DDSP_HPDA ==> HDMIA_HPD */
  54         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
  55         /* E18 : DDP1_CTRLCLK ==> NC */
  56         PAD_NC(GPP_E18, NONE),
  57         /* E20 : DDP2_CTRLCLK ==> DDIA_HDMI_CTRLCLK */
  58         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
  59         /* E21 : DDP2_CTRLDATA ==> DDIA_HDMI_CTRLDATA */
  60         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
  61
  62         /* F11 : THC1_SPI2_CLK ==> NC */
  63         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
  64         /* F12 : GSXDOUT ==> NC */
  65         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  66         /* F13 : GSXDOUT ==> NC */
  67         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
  68         /* F15 : GSXSRESET# ==> NC */
  69         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  70         /* F16 : GSXCLK ==> NC */
  71         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
  72
  73         /* H19 : SRCCLKREQ4# ==> CLKREQ_4 */
  74         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
  75         /* H21 : IMGCLKOUT2 ==>  EMMC_PE_WAKE_ODL */
  76         PAD_CFG_GPO(GPP_H21, 1, DEEP),
  77
  78         /* R4 : HDA_RST# ==> NC */
  79         PAD_NC(GPP_R4, NONE),
  80         /* R5 : HDA_SDI1 ==> NC */
  81         PAD_NC(GPP_R5, NONE),
  82         /* R6 : I2S2_TXD ==> NC */
  83         PAD_NC(GPP_R6, NONE),
  84         /* R7 : I2S2_RXD ==> NC */
  85         PAD_NC(GPP_R7, NONE),
  86 };
  87
  88 /* Early pad configuration in bootblock */
  89 static const struct pad_config early_gpio_table[] = {
  90         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  91         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  92         /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */
  93         PAD_CFG_GPO(GPP_A21, 1, DEEP),
  94         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
  95         PAD_CFG_GPO(GPP_B3, 0, DEEP),
  96         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  97         PAD_CFG_GPO(GPP_B4, 0, DEEP),
  98         /* E15 : RSVD_TP ==> PCH_WP_OD */
  99         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 100         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 101         PAD_CFG_GPO(GPP_F14, 1, DEEP),
 102         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 103         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 104         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 105         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 106         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 107         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 108         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 109         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 110         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 111         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 112         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 113         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 114
 115         /* CPU PCIe VGPIO for PEG60 */
 116         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 117         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 118         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 119         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 120         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 121         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 122         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 123         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 124         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 125         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 126         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 127         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 128         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 129         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 130         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 131         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 132         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 133         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 134         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 135         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 136 };
 137
 138 static const struct pad_config romstage_gpio_table[] = {
 139         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
 140         PAD_CFG_GPO(GPP_B3, 1, DEEP),
 141         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 142         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 143 };
 144
 145 const struct pad_config *variant_gpio_override_table(size_t *num)
 146 {
 147         *num = ARRAY_SIZE(override_gpio_table);
 148         return override_gpio_table;
 149 }
 150
 151 const struct pad_config *variant_early_gpio_table(size_t *num)
 152 {
 153         *num = ARRAY_SIZE(early_gpio_table);
 154         return early_gpio_table;
 155 }
 156
 157 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 158 {
 159         *num = ARRAY_SIZE(romstage_gpio_table);
 160         return romstage_gpio_table;
 161 }