src/mainboard/google/brya/variants/marasov/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <boardid.h>
   5 #include <soc/gpio.h>
   6
   7 /* Pad configuration in ramstage */
   8 static const struct pad_config override_gpio_table[] = {
   9         /* A5  : ESPI_ALERT0# ==> NC */
  10         PAD_NC(GPP_A5, NONE),
  11         /* A6  : ESPI_ALERT1# ==> NC */
  12         PAD_NC(GPP_A6, NONE),
  13         /* A7  : SRCCLK_OE7# ==> NC */
  14         PAD_NC(GPP_A7, NONE),
  15         /* A8  : WWAN_RF_DISABLE_ODL ==> NC */
  16         PAD_NC(GPP_A8, NONE),
  17         /* A9  : ESPI_CLK ==> ESPI_CLK */
  18         PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
  19         /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
  20         PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
  21         /* A12 : EN_PP3300_WWAN ==> NC */
  22         PAD_NC(GPP_A12, NONE),
  23         /* A19 : USB_C2_AUX_DC_P ==> NC */
  24         PAD_NC(GPP_A19, NONE),
  25         /* A20 : USB_C2_AUX_DC_N ==> NC */
  26         PAD_NC(GPP_A20, NONE),
  27         /* A21 : USB_C1_AUX_DC_P ==> NC */
  28         PAD_NC(GPP_A21, NONE),
  29         /* A22 : USB_C1_AUX_DC_N ==> NC */
  30         PAD_NC(GPP_A22, NONE),
  31         /* B2  : GPP_B2(TP97) ==> GPP_B2(TP1712) */
  32         PAD_NC(GPP_B2, NONE),
  33         /* B3  : PROC_GP2 ==> NC */
  34         PAD_NC(GPP_B3, NONE),
  35         /* B5  : PCH_I2C_MISC_SDA ==> NC */
  36         PAD_NC(GPP_B5, NONE),
  37         /* B6  : PCH_I2C_MISC_SCL ==> NC */
  38         PAD_NC(GPP_B6, NONE),
  39         /* B7  : PCH_I2C_TCHSCR_SDA ==> PCH_I2C_TCHSCR_SDA */
  40         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  41         /* B8  : PCH_I2C_TCHSCR_SCL ==> PCH_I2C_TCHSCR_SCL */
  42         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  43         /* B15 : FP_USER_PRES_FP_L ==> NC */
  44         PAD_NC(GPP_B15, NONE),
  45         /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
  46         PAD_CFG_NF_LOCK(GPP_B23, DN_20K, NF2, LOCK_CONFIG),
  47         /* C3  : EN_UCAM_PWR ==> EN_UCAM_PWR(TP1103) */
  48         PAD_NC(GPP_C3, NONE),
  49         /* C4  : EN_UCAM_SENR_PWR ==> EN_UCAM_SENR_PWR(TP1104) */
  50         PAD_NC(GPP_C4, NONE),
  51         /* D0  : ISH_GP0 ==> NC */
  52         PAD_NC(GPP_D0, NONE),
  53         /* D3  : ISH_GP3 ==> NC */
  54         PAD_NC(GPP_D3, NONE),
  55         /* D5  : WWAN_DPR_SAR_ODL ==> NC */
  56         PAD_NC(GPP_D5, NONE),
  57         /* D8  : SD_CLKREQ_ODL ==> NC */
  58         PAD_NC(GPP_D8, NONE),
  59         /* D9  : USB_C2_LSX_TX ==> NC */
  60         PAD_NC(GPP_D9, NONE),
  61         /* D10 : ISH_SPI_CLK ==> NC */
  62         PAD_NC(GPP_D10, NONE),
  63         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
  64         PAD_CFG_GPO(GPP_D11, 1, DEEP),
  65         /* D13 : ISH_UART0_RXD ==> NC */
  66         PAD_NC(GPP_D13, NONE),
  67         /* D14 : ISH_UART0_TXD ==> NC */
  68         PAD_NC(GPP_D14, NONE),
  69         /* D15 : ISH_UART0_RTS# ==> NC */
  70         PAD_NC(GPP_D15, NONE),
  71         /* D16 : ISH_UART0_CTS# ==> NC */
  72         PAD_NC(GPP_D16, NONE),
  73         /* D17 : UART1_RXD ==> NC */
  74         PAD_NC(GPP_D17, NONE),
  75         /* D18 : UART1_TXD ==> NC */
  76         PAD_NC(GPP_D18, NONE),
  77         /* E0 : WWAN_PERST_L ==> NC */
  78         PAD_NC(GPP_E0, NONE),
  79         /* E3  : PROC_GP0 ==> NC */
  80         PAD_NC(GPP_E3, NONE),
  81         /* E4  : SATA_DEVSLP0 ==> NC */
  82         PAD_NC(GPP_E4, NONE),
  83         /* E5  : SATA_DEVSLP1 ==> NC */
  84         PAD_NC(GPP_E5, NONE),
  85         /* E7  : PROC_GP1 ==> NC */
  86         PAD_NC(GPP_E7, NONE),
  87         /* E10 : WWAN_CONFIG0 ==> NC */
  88         PAD_NC(GPP_E10, NONE),
  89         /* E16 : WWAN_RST_L ==> NC */
  90         PAD_NC(GPP_E16, NONE),
  91         /* E17 : WWAN_CONFIG2 ==> SSD_STRAP */
  92         PAD_CFG_GPI(GPP_E17, NONE, DEEP),
  93         /* E18 : USB_C0_LSX_TX ==> NC */
  94         PAD_NC(GPP_E18, NONE),
  95         /* E19 : DDP1_CTRLDATA ==> NC */
  96         PAD_NC(GPP_E19, NONE),
  97         /* E20 : USB_C1_LSX_TX ==> NC */
  98         PAD_NC(GPP_E20, NONE),
  99         /* E21 : DDP2_CTRLDATA ==> NC */
 100         PAD_NC(GPP_E21, NONE),
 101         /* F6  : WWAN_WLAN_COEX3 ==> NC */
 102         PAD_NC(GPP_F6, NONE),
 103         /* F11 : THC1_SPI2_CLK ==> NC */
 104         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 105         /* F12 : GSXDOUT ==> NC */
 106         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 107         /* F13 : GSXDOUT ==> NC */
 108         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 109         /* F15 : GSXSRESET# ==> NC */
 110         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 111         /* F16 : GSXCLK ==> NC */
 112         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 113         /* F19 : GPP_F19(TP93) ==> NC */
 114         PAD_NC(GPP_F19, NONE),
 115         /* F20 : UCAM_RST_L ==> NC */
 116         PAD_NC(GPP_F20, NONE),
 117         /* F21 : WWAN_FCPO_L ==> NC */
 118         PAD_NC(GPP_F21, NONE),
 119         /* F23 : NC */
 120         PAD_CFG_NF_LOCK(GPP_F23, NONE, NF1, LOCK_CONFIG),
 121         /* H8  : WWAN_WLAN_COEX1 ==> PCB_ID0(NC) */
 122         PAD_CFG_GPI_LOCK(GPP_H8, NONE, LOCK_CONFIG),
 123         /* H9  : WWAN_WLAN_COEX2 ==> PCB_ID1(NC) */
 124         PAD_CFG_GPI_LOCK(GPP_H9, NONE, LOCK_CONFIG),
 125         /* H12 : I2C7_SDA ==> NC */
 126         PAD_NC(GPP_H12, NONE),
 127         /* H19 : SRCCLKREQ4# ==> NC */
 128         PAD_NC(GPP_H19, NONE),
 129         /* H21 : UCAM_MCLK ==>  NC */
 130         PAD_NC(GPP_H21, NONE),
 131         /* H22 : WCAM_MCLK ==> NC */
 132         PAD_NC(GPP_H22, NONE),
 133         /* H23 : WWAN_CLKREQ_ODL ==> NC */
 134         PAD_NC(GPP_H23, NONE),
 135         /* R4 : HDA_RST# ==> NC */
 136         PAD_NC(GPP_R4, NONE),
 137         /* R5 : HDA_SDI1 ==> NC */
 138         PAD_NC(GPP_R5, NONE),
 139         /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */
 140         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 141         /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */
 142         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 143         /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */
 144         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 145         /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */
 146         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 147         /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */
 148         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 149         /* S3 : SNDW1_DATA ==> NC */
 150         PAD_NC(GPP_S3, NONE),
 151         /* S4 : SDW_SPKR_CLK ==> NC */
 152         PAD_NC(GPP_S4, NONE),
 153         /* S5 : SDW_SPKR_DATA ==> NC */
 154         PAD_NC(GPP_S5, NONE),
 155         /* S6 : DMIC_CLK1_R ==> NC */
 156         PAD_NC(GPP_S6, NONE),
 157         /* S7 : DMIC_DATA1_R ==> NC */
 158         PAD_NC(GPP_S7, NONE),
 159         /* GPD11: LANPHYC ==> NC */
 160         PAD_NC(GPD11, NONE),
 161 };
 162
 163 /* Early pad configuration in bootblock */
 164 static const struct pad_config early_gpio_table[] = {
 165         /* A13 : GSC_PCH_INT_ODL ==> GSC_PCH_INT_ODL */
 166         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 167         /* B4  : SSD_PERST_L ==> SSD_PERST_L */
 168         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 169         /* B7  : PCH_I2C_TCHSCR_SDA ==> PCH_I2C_TCHSCR_SDA */
 170         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 171         /* B8  : PCH_I2C_TCHSCR_SCL ==> PCH_I2C_TCHSCR_SCL */
 172         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 173
 174         /*
 175          * D1  : FP_RST_ODL ==> FP_RST_ODL
 176          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 177          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 178          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 179          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 180          * FPMCU not working after a S3 resume. This is a known issue.
 181          */
 182         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 183         /* D2  : EN_FP_PWR ==> EN_FP_PWR */
 184         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 185         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 186         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 187         /* E0  : WWAN_PERST_L ==> NC */
 188         PAD_NC(GPP_E0, NONE),
 189         /* E13 : MEM_CH_SEL ==> MEM_CH_SEL */
 190         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 191         /* E15 : PCH_WP_OD ==> PCH_WP_OD */
 192         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 193         /* E16 : WWAN_RST_L ==> NC */
 194         PAD_NC(GPP_E16, NONE),
 195         /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */
 196         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 197         /* H6  : PCH_I2C_TPM_SDA ==> PCH_I2C_TPM_SDA */
 198         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 199         /* H7  : PCH_I2C_TPM_SCL ==> PCH_I2C_TPM_SCL */
 200         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 201         /* H10 : UART_PCH_RX_DBG_TX ==> UART_PCH_RX_DBG_TX */
 202         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 203         /* H11 : UART_PCH_TX_DBG_RX ==> UART_PCH_TX_DBG_RX */
 204         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 205         /* H13 : EN_PP3300_SD ==> EN_PP3300_SD(TP1201) */
 206         PAD_NC(GPP_H13, UP_20K),
 207 };
 208
 209 static const struct pad_config romstage_gpio_table[] = {
 210         /* B4  : SSD_PERST_L ==> SSD_PERST_L */
 211         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 212
 213         /* Enable touchscreen, hold in reset */
 214         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 215         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 216         /* C1  : SMBDATA ==> USI_RST_L */
 217         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 218
 219         /* D1  : FP_RST_ODL ==> FP_RST_ODL */
 220         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 221         /* D2  : EN_FP_PWR ==> EN_FP_PWR */
 222         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 223 };
 224
 225 const struct pad_config *variant_gpio_override_table(size_t *num)
 226 {
 227         *num = ARRAY_SIZE(override_gpio_table);
 228         return override_gpio_table;
 229 }
 230
 231 const struct pad_config *variant_early_gpio_table(size_t *num)
 232 {
 233         *num = ARRAY_SIZE(early_gpio_table);
 234         return early_gpio_table;
 235 }
 236
 237 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 238 {
 239         *num = ARRAY_SIZE(romstage_gpio_table);
 240         return romstage_gpio_table;
 241 }