src/mainboard/google/brya/variants/mithrax/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A7  : SRCCLK_OE7# ==> PEN_DET_ODL */
  11         PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, NONE, DEEP),
  12         /* A8  : SRCCLKREQ7# ==> PEN_DET_ODL */
  13         PAD_CFG_GPI_SCI_HIGH(GPP_A8, NONE, DEEP, EDGE_SINGLE),
  14         /* B3  : PROC_GP2 ==> NC */
  15         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  16         /* B5  : ISH_I2C0_SDA ==> NC */
  17         PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
  18         /* B6  : ISH_I2C0_SCL ==> NC */
  19         PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
  20         /* B6  : TIME_SYNC0 ==> NC */
  21         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  22         /* C3 : SML0CLK ==> NC */
  23         PAD_NC(GPP_C3, NONE),
  24         /* C4 : SML0DATA ==> EN_PP5000_PEN */
  25         PAD_CFG_GPO(GPP_C4, 1, DEEP),
  26         /* D0  : ISH_GP0 ==> NC */
  27         PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
  28         /* D1  : ISH_GP1 ==> NC */
  29         PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
  30         /* D2  : ISH_GP2 ==> NC */
  31         PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
  32         /* D3  : ISH_GP3 ==> NC */
  33         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  34         /* D5  : SRCCLKREQ0# ==> NC */
  35         PAD_NC(GPP_D5, NONE),
  36         /* D15 : ISH_UART0_RTS# ==> NC */
  37         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  38         /* D16 : ISH_UART0_CTS# ==> NC */
  39         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  40         /* E0  : SATAXPCIE0 ==> NC */
  41         PAD_NC(GPP_E0, NONE),
  42         /* E3  : PROC_GP0 ==> NC */
  43         PAD_NC(GPP_E3, NONE),
  44         /* E7  : PROC_GP1 ==> NC */
  45         PAD_NC(GPP_E7, NONE),
  46         /* E9  : USB_OC0# ==> NC */
  47         PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
  48         /* E10 : THC0_SPI1_CS# ==> NC */
  49         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
  50         /* E16 : RSVD_TP ==> NC */
  51         PAD_NC(GPP_E16, NONE),
  52         /* E17 : THC0_SPI1_INT# ==> NC */
  53         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
  54         /* E18 : DDP1_CTRLCLK ==> NC */
  55         PAD_NC(GPP_E18, NONE),
  56         /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
  57         PAD_NC(GPP_E19, NONE),
  58         /* E22 : DDPA_CTRLCLK ==> NC */
  59         PAD_NC(GPP_E22, NONE),
  60         /* E23 : DDPA_CTRLDATA ==> NC */
  61         PAD_NC(GPP_E23, NONE),
  62         /* F6  : CNV_PA_BLANKING ==> NC */
  63         PAD_NC(GPP_F6, NONE),
  64         /* F11 : THC1_SPI2_CLK ==> NC */
  65         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
  66         /* F12 : GSXDOUT ==> NC */
  67         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  68         /* F13 : GSXDOUT ==> NC */
  69         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
  70         /* F15 : GSXSRESET# ==> NC */
  71         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  72         /* F16 : GSXCLK ==> NC */
  73         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
  74         /* F20 : EXT_PWR_GATE# ==> NC */
  75         PAD_NC(GPP_F20, NONE),
  76         /* F21 : EXT_PWR_GATE2# ==> NC */
  77         PAD_NC(GPP_F21, NONE),
  78         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  79         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
  80         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  81         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
  82         /* H8  : I2C4_SDA ==> NC */
  83         PAD_NC(GPP_H8, NONE),
  84         /* H9  : I2C4_SCL ==> NC */
  85         PAD_NC(GPP_H9, NONE),
  86         /* H19 : SRCCLKREQ4# ==> NC */
  87         PAD_NC(GPP_H19, NONE),
  88         /* H21 : IMGCLKOUT2 ==>  NC */
  89         PAD_NC(GPP_H21, NONE),
  90         /* H22 : IMGCLKOUT3 ==> NC */
  91         PAD_NC(GPP_H22, NONE),
  92         /* H23 : SRCCLKREQ5# ==> NC */
  93         PAD_NC(GPP_H23, NONE),
  94         /* R4 : HDA_RST# ==> DMIC_CLK0 */
  95         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
  96         /* R5 : HDA_SDI1 ==> DMIC_DATA0 */
  97         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
  98         /* R6 : I2S2_TXD ==> NC */
  99         PAD_NC(GPP_R6, NONE),
 100         /* R7 : I2S2_RXD ==> NC */
 101         PAD_NC(GPP_R7, NONE),
 102         /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */
 103         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 104         /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */
 105         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 106         /* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */
 107         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 108         /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */
 109         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
 110         /* S4 : SNDW2_CLK ==> NC */
 111         PAD_NC(GPP_S4, NONE),
 112         /* S5 : SNDW2_DATA ==> NC */
 113         PAD_NC(GPP_S5, NONE),
 114
 115 };
 116
 117 /* Early pad configuration in bootblock */
 118 static const struct pad_config early_gpio_table[] = {
 119         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 120         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 121         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 122         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 123         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 124         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 125         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 126         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 127         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 128         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 129         /* D18 : UART1_TXD ==> SD_PE_RST_L */
 130         PAD_CFG_GPO(GPP_D18, 0, PLTRST),
 131         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 132         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 133         /* E15 : RSVD_TP ==> PCH_WP_OD */
 134         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 135         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 136         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 137         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 138         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 139         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 140         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 141         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 142         PAD_CFG_GPO(GPP_H13, 1, PLTRST),
 143 };
 144
 145 static const struct pad_config romstage_gpio_table[] = {
 146         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 147         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 148
 149         /* Enable touchscreen, hold in reset */
 150         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 151         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 152         /* C1  : SMBDATA ==> USI_RST_L */
 153         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 154 };
 155
 156 const struct pad_config *variant_gpio_override_table(size_t *num)
 157 {
 158         *num = ARRAY_SIZE(override_gpio_table);
 159         return override_gpio_table;
 160 }
 161
 162 const struct pad_config *variant_early_gpio_table(size_t *num)
 163 {
 164         *num = ARRAY_SIZE(early_gpio_table);
 165         return early_gpio_table;
 166 }
 167
 168 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 169 {
 170         *num = ARRAY_SIZE(romstage_gpio_table);
 171         return romstage_gpio_table;
 172 }