src/mainboard/google/brya/variants/nova/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A14 : USB_OC1# ==> NC */
  11         PAD_NC(GPP_A14, NONE),
  12         /* A15 : USB_OC2# ==> NC */
  13         PAD_NC(GPP_A15, NONE),
  14         /* A19 : DDSP_HPD1 ==> NC */
  15         PAD_NC(GPP_A19, NONE),
  16         /* A20 : DDSP_HPD2 ==> NC */
  17         PAD_NC(GPP_A20, NONE),
  18         /* A21 : DDPC_CTRCLK ==> NC */
  19         PAD_NC(GPP_A21, NONE),
  20         /* A22 : DDPC_CTRLDATA ==> NC */
  21         PAD_NC(GPP_A22, NONE),
  22
  23         /* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
  24         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  25         /* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
  26         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  27         /* B15 : TIME_SYNC0 ==> HP_INT_L */
  28         PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, EDGE_BOTH),
  29         /* B16 : I2C5_SDA ==> PCH_I2C_TPU_SDA */
  30         PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
  31         /* B17 : I2C5_SCL ==> PCH_I2C_TPU_SCL */
  32         PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
  33
  34         /* C0 : SMBCLK ==> NC */
  35         PAD_NC(GPP_C0, NONE),
  36         /* C1 : SMBDATA ==> NC */
  37         PAD_NC(GPP_C1, NONE),
  38         /* C3 : SML0CLK ==> NC */
  39         PAD_NC(GPP_C3, NONE),
  40         /* C4 : SML0DATA ==> SMBUS_ISP_SCALAR */
  41         PAD_CFG_GPO(GPP_C4, 0, DEEP),
  42
  43         /* D0  : ISH_GP0 ==> BOOT_SEL_N */
  44         PAD_CFG_GPO_LOCK(GPP_D0, 1, LOCK_CONFIG),
  45         /* D1  : ISH_GP1 ==> REC_MODE */
  46         PAD_NC(GPP_D1, NONE),
  47         /* D2  : ISH_GP2 ==> DEV_MODE_CTRL */
  48         PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG),
  49         /* D3  : ISH_GP3 ==> BOOT_IND */
  50         PAD_NC(GPP_D3, NONE),
  51         /* D9  : ISH_SPI_CS# ==> NC */
  52         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  53         /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
  54         PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG),
  55         /* D13 : ISH_UART0_RXD ==> NC */
  56         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  57         /* D14 : ISH_UART0_TXD ==> QSPI_MR_N */
  58         PAD_CFG_GPO_LOCK(GPP_D14, 1, LOCK_CONFIG),
  59         /* D15 : ISH_UART0_RTS# ==> USI_RST_L */
  60         PAD_CFG_GPO(GPP_D15, 1, DEEP),
  61         /* D16 : ISH_UART0_CTS# ==> USI_INT */
  62         PAD_CFG_GPI_IRQ_WAKE(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
  63         /* D17 : UART1_RXD ==> PCH_RX_TSUM_UART_TX */
  64         PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
  65         /* D18 : UART1_TXD ==> PCH_TX_TSUM_UART_RX */
  66         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
  67
  68         /* E4  : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
  69         PAD_CFG_GPI_LOCK(GPP_E4, NONE, LOCK_CONFIG),
  70         /* E5  : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */
  71         PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
  72         /* E9  : USB_OC0# ==> USB_C0_OC_ODL */
  73         PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
  74         /* E18 : DDP1_CTRLCLK ==> NC */
  75         PAD_NC(GPP_E18, NONE),
  76         /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
  77         PAD_CFG_GPI_LOCK(GPP_E19, NONE, LOCK_CONFIG),
  78         /* E20 : DDP2_CTRLCLK ==> NC */
  79         PAD_NC(GPP_E20, NONE),
  80         /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
  81         PAD_CFG_GPI_LOCK(GPP_E21, NONE, LOCK_CONFIG),
  82
  83         /* F11 : THC1_SPI2_CLK ==> MEM_CH_SEL */
  84         PAD_CFG_GPI_LOCK(GPP_F11, NONE, LOCK_CONFIG),
  85         /* F12 : GSXDOUT ==> MEM_STRAP_1 */
  86         PAD_CFG_GPI_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  87         /* F13 : GSXDOUT ==> MEM_STRAP_2 */
  88         PAD_CFG_GPI_LOCK(GPP_F13, NONE, LOCK_CONFIG),
  89         /* F15 : GSXSRESET# ==> MEM_STRAP_3 */
  90         PAD_CFG_GPI_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  91         /* F16 : GSXCLK ==> MEM_STRAP_0 */
  92         PAD_CFG_GPI_LOCK(GPP_F16, NONE, LOCK_CONFIG),
  93
  94         /* H4  : I2C0_SDA ==> PCH_I2C_SCALER_SDA */
  95         PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
  96         /* H5  : I2C0_SCL ==> PCH_I2C_SCALER_SCL */
  97         PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
  98         /* H12 : I2C7_SDA ==> NC */
  99         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
 100         /* H13 : I2C7_SCL ==> NC */
 101         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
 102         /* H15 : DDPB_CTRLCLK ==> NC */
 103         PAD_NC(GPP_H15, NONE),
 104         /* H17 : DDPB_CTRLDATA ==> NC */
 105         PAD_NC(GPP_H17, NONE),
 106         /* H19 : SRCCLKREQ4# ==> M2_TPU1_CLKREQ_ODL */
 107         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 108
 109         /* R0 : HDA_BCLK ==> NC */
 110         PAD_NC_LOCK(GPP_R0, NONE, LOCK_CONFIG),
 111         /* R1 : HDA_SYNC ==> I2S_PCH_TX_HP_RX_STRAP */
 112         PAD_CFG_GPI_LOCK(GPP_R1, NONE, LOCK_CONFIG),
 113         /* R2 : HDA_SDO ==> NC */
 114         PAD_NC(GPP_R2, NONE),
 115         /* R3 : HDA_SDIO ==> NC */
 116         PAD_NC(GPP_R3, NONE),
 117         /* R4 : HDA_RST# ==> NC */
 118         PAD_NC(GPP_R4, NONE),
 119         /* R5 : HDA_SDI1 ==> NC */
 120         PAD_NC(GPP_R5, NONE),
 121         /* R6 : I2S2_TXD ==> NC */
 122         PAD_NC(GPP_R6, NONE),
 123         /* R7 : I2S2_RXD ==> NC */
 124         PAD_NC(GPP_R7, NONE),
 125
 126         /* S0 : SNDW0_CLK ==> PCH_I2S_SCLK_MX8M */
 127         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 128         /* S1 : SNDW0_DATA ==> PCH_I2S_SFRM_MX8M */
 129         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 130         /* S2 : SNDW1_CLK ==> PCH_I2S_TX_MX8M_RX */
 131         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 132         /* S3 : SNDW1_DATA ==> PCH_I2S_RX_MX8M_TX */
 133         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
 134 };
 135
 136 /* Early pad configuration in bootblock */
 137 static const struct pad_config early_gpio_table[] = {
 138         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 139         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 140         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 141         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 142         /* E15 : RSVD_TP ==> PCH_WP_OD */
 143         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 144         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 145         PAD_CFG_GPO(GPP_F14, 1, DEEP),
 146         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 147         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 148         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 149         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 150         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 151         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 152         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 153         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 154         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 155         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 156
 157         /* CPU PCIe VGPIO for PEG60 */
 158         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 159         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 160         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 161         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 162         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 163         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 164         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 165         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 166         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 167         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 168         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 169         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 170         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 171         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 172         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 173         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 174         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 175         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 176         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 177         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 178 };
 179
 180 static const struct pad_config romstage_gpio_table[] = {
 181         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 182         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 183 };
 184
 185 const struct pad_config *variant_gpio_override_table(size_t *num)
 186 {
 187         *num = ARRAY_SIZE(override_gpio_table);
 188         return override_gpio_table;
 189 }
 190
 191 const struct pad_config *variant_early_gpio_table(size_t *num)
 192 {
 193         *num = ARRAY_SIZE(early_gpio_table);
 194         return early_gpio_table;
 195 }
 196
 197 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 198 {
 199         *num = ARRAY_SIZE(romstage_gpio_table);
 200         return romstage_gpio_table;
 201 }