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mb/google/brya/var/orisa: Update Type C DisplayPort HPD Configuration
[coreboot2.git] / src / mainboard / google / brya / variants / nova / overridetree.cb
blobbf517c87b030bf2726fbbe5baca184519fd3b870
1 chip soc/intel/alderlake
2 register "domain_vr_config[VR_DOMAIN_IA]" = "{
3 .enable_fast_vmode = 1,
4 }"
5
6 register "sagv" = "SaGv_Enabled"
7
8 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port C0
9 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
10 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3
11 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2
12 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
13 register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5
14 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6
15 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
16 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
17
18 register "usb3_ports[0]" = "{
19 .enable = 1,
20 .ocpin = OC_SKIP,
21 .tx_de_emp = 0x2B,
22 .tx_downscale_amp = 0x00,
23 }" # Type-A port A2
24 register "usb3_ports[1]" = "{
25 .enable = 1,
26 .ocpin = OC_SKIP,
27 .tx_de_emp = 0x2B,
28 .tx_downscale_amp = 0x00,
29 }" # Type-A port A3
30
31 register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable Type-A port
32 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port
33
34 register "tcss_ports[0]" = "TCSS_PORT_EMPTY"
35 register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
36 register "tcss_ports[2]" = "TCSS_PORT_EMPTY"
37 register "tcss_ports[3]" = "TCSS_PORT_EMPTY"
38
39 register "serial_io_i2c_mode" = "{
40 [PchSerialIoIndexI2C0] = PchSerialIoPci,
41 [PchSerialIoIndexI2C1] = PchSerialIoPci,
42 [PchSerialIoIndexI2C2] = PchSerialIoPci,
43 [PchSerialIoIndexI2C3] = PchSerialIoPci,
44 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
45 [PchSerialIoIndexI2C5] = PchSerialIoPci,
46 }"
47
48 register "serial_io_gspi_mode" = "{
49 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
50 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
51 }"
52
53 register "serial_io_uart_mode" = "{
54 [PchSerialIoIndexUART0] = PchSerialIoPci,
55 [PchSerialIoIndexUART1] = PchSerialIoSkipInit,
56 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
57 }"
58
59 register "ddi_ports_config" = "{
60 [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
61 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
62 }"
63
64 # Intel Common SoC Config
65 #+-------------------+---------------------------+
66 #| Field | Value |
67 #+-------------------+---------------------------+
68 #| I2C0 | Scaler |
69 #| I2C1 | cr50 TPM. Early init is |
70 #| | required to set up a BAR |
71 #| | for TPM communication |
72 #| I2C2 | HDMI_A |
73 #| I2C3 | Touchscreen |
74 #| I2C5 | TPU |
75 #+-------------------+---------------------------+
76 register "common_soc_config" = "{
77 .i2c[0] = {
78 .speed = I2C_SPEED_FAST,
79 },
80 .i2c[1] = {
81 .early_init = 1,
82 .speed = I2C_SPEED_FAST,
83 .rise_time_ns = 600,
84 .fall_time_ns = 400,
85 .data_hold_time_ns = 50,
86 },
87 .i2c[2] = {
88 .speed = I2C_SPEED_FAST,
89 },
90 .i2c[3] = {
91 .speed = I2C_SPEED_FAST,
92 .rise_time_ns = 650,
93 .fall_time_ns = 400,
94 .data_hold_time_ns = 50,
95 },
96 .i2c[5] = {
97 .speed = I2C_SPEED_FAST,
98 },
99 }"
100
101 device domain 0 on
102 device ref dtt on
103 chip drivers/intel/dptf
104 ## sensor information
105 register "options.tsr[0].desc" = ""DRAM""
106 register "options.tsr[1].desc" = ""Charger""
107
108 # TODO: below values are initial reference values only
109 ## Active Policy
110 register "policies.active" = "{
111 [0] = {
112 .target = DPTF_CPU,
113 .thresholds = {
114 TEMP_PCT(85, 90),
115 TEMP_PCT(80, 80),
116 TEMP_PCT(75, 70),
117 }
118 }
119 }"
120
121 ## Passive Policy
122 register "policies.passive" = "{
123 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
124 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
125 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
126 }"
127
128 ## Critical Policy
129 register "policies.critical" = "{
130 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
131 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
132 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
133 }"
134
135 register "controls.power_limits" = "{
136 .pl1 = {
137 .min_power = 3000,
138 .max_power = 15000,
139 .time_window_min = 28 * MSECS_PER_SEC,
140 .time_window_max = 32 * MSECS_PER_SEC,
141 .granularity = 200,
142 },
143 .pl2 = {
144 .min_power = 55000,
145 .max_power = 55000,
146 .time_window_min = 28 * MSECS_PER_SEC,
147 .time_window_max = 32 * MSECS_PER_SEC,
148 .granularity = 1000,
149 }
150 }"
151
152 ## Charger Performance Control (Control, mA)
153 register "controls.charger_perf" = "{
154 [0] = { 255, 1700 },
155 [1] = { 24, 1500 },
156 [2] = { 16, 1000 },
157 [3] = { 8, 500 }
158 }"
159
160 ## Fan Performance Control (Percent, Speed, Noise, Power)
161 register "controls.fan_perf" = "{
162 [0] = { 90, 6700, 220, 2200, },
163 [1] = { 80, 5800, 180, 1800, },
164 [2] = { 70, 5000, 145, 1450, },
165 [3] = { 60, 4900, 115, 1150, },
166 [4] = { 50, 3838, 90, 900, },
167 [5] = { 40, 2904, 55, 550, },
168 [6] = { 30, 2337, 30, 300, },
169 [7] = { 20, 1608, 15, 150, },
170 [8] = { 10, 800, 10, 100, },
171 [9] = { 0, 0, 0, 50, }
172 }"
173
174 ## Fan options
175 register "options.fan.fine_grained_control" = "1"
176 register "options.fan.step_size" = "2"
177
178 device generic 0 alias dptf_policy on end
179 end
180 end
181 device ref pcie4_0 on
182 # Enable CPU PCIE RP 1 using CLK 0
183 register "cpu_pcie_rp[CPU_RP(1)]" = "{
184 .clk_req = 0,
185 .clk_src = 0,
186 .flags = PCIE_RP_LTR | PCIE_RP_AER,
187 }"
188 end
189 device ref cnvi_wifi on
190 chip drivers/wifi/generic
191 register "wake" = "GPE0_PME_B0"
192 device generic 0 on end
193 end
194 end
195 device ref i2c0 on end # Scaler
196 device ref i2c1 on
197 chip drivers/i2c/tpm
198 register "hid" = ""GOOG0005""
199 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
200 device i2c 50 on end
201 end
202 end #TPM
203 device ref i2c2 on end # HDMI_A
204 device ref i2c3 on
205 chip drivers/i2c/hid
206 register "generic.hid" = ""ILTK0001""
207 register "generic.desc" = ""ILITEK Touchscreen""
208 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
209 register "generic.detect" = "1"
210 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
211 register "generic.reset_delay_ms" = "200"
212 register "generic.enable_delay_ms" = "12"
213 register "generic.has_power_resource" = "1"
214 register "hid_desc_reg_offset" = "0x01"
215 device i2c 41 on end
216 end
217 end # Touch screen
218 device ref i2c5 on end # TPU
219 device ref pcie_rp6 on
220 # Enable PCIE 6 using clk 3
221 register "pch_pcie_rp[PCH_RP(6)]" = "{
222 .clk_src = 3,
223 .clk_req = 3,
224 .flags = PCIE_RP_LTR | PCIE_RP_AER,
225 }"
226 end #TPU0
227 device ref pcie_rp7 on
228 # Enable PCIE 7 using clk 6
229 register "pch_pcie_rp[PCH_RP(7)]" = "{
230 .clk_src = 6,
231 .clk_req = 6,
232 .flags = PCIE_RP_LTR | PCIE_RP_AER,
233 }"
234 chip drivers/net
235 register "customized_leds" = "0x05af"
236 register "wake" = "GPE0_DW0_07" # GPP_A7
237 register "device_index" = "0"
238 register "enable_aspm_l1_2" = "1"
239 device pci 00.0 on end
240 end
241 end # RTL8111H Ethernet NIC
242 device ref pcie_rp8 on
243 # Enable PCIE 8 using clk 4
244 register "pch_pcie_rp[PCH_RP(8)]" = "{
245 .clk_src = 4,
246 .clk_req = 4,
247 .flags = PCIE_RP_LTR | PCIE_RP_AER,
248 }"
249 end #TPU1
250 device ref uart0 on end
251 device ref uart1 on end
252 device ref gspi0 off end
253 device ref gspi1 off end
254 device ref pch_espi on
255 chip ec/google/chromeec
256 device pnp 0c09.0 on end
257 end
258 end
259 device ref pmc hidden end
260 device ref tbt_pcie_rp0 off end
261 device ref tbt_pcie_rp1 off end
262 device ref tbt_pcie_rp2 off end
263 device ref tbt_pcie_rp3 off end
264 device ref tcss_xhci on end
265 device ref tcss_dma0 off end
266 device ref tcss_dma1 off end
267 device ref xhci on
268 chip drivers/usb/acpi
269 device ref xhci_root_hub on
270 chip drivers/usb/acpi
271 register "desc" = ""Type-C Charging Port C0 (MLB)""
272 register "type" = "UPC_TYPE_PROPRIETARY"
273 register "use_custom_pld" = "true"
274 register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(0, 2))"
275 device ref usb2_port1 on end
276 end
277 chip drivers/usb/acpi
278 register "desc" = ""USB2 Type-A Port A3 (MLB)""
279 register "type" = "UPC_TYPE_A"
280 register "use_custom_pld" = "true"
281 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(0, 1))"
282 device ref usb2_port3 on end
283 end
284 chip drivers/usb/acpi
285 register "desc" = ""USB2 Type-A Port A2 (MLB)""
286 register "type" = "UPC_TYPE_A"
287 register "use_custom_pld" = "true"
288 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(0, 0))"
289 device ref usb2_port4 on end
290 end
291 chip drivers/usb/acpi
292 register "desc" = ""USB2 Bluetooth""
293 register "type" = "UPC_TYPE_INTERNAL"
294 register "reset_gpio" =
295 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
296 device ref usb2_port10 on end
297 end
298 chip drivers/usb/acpi
299 register "desc" = ""USB3 Type-A Port A2 (MLB)""
300 register "type" = "UPC_TYPE_USB3_A"
301 register "use_custom_pld" = "true"
302 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(0, 0))"
303 device ref usb3_port1 on end
304 end
305 chip drivers/usb/acpi
306 register "desc" = ""USB3 Type-A Port A3 (MLB)""
307 register "type" = "UPC_TYPE_USB3_A"
308 register "use_custom_pld" = "true"
309 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(0, 1))"
310 device ref usb3_port2 on end
311 end
312 end
313 end
314 end
315 end
316
317 end
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