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mb/google/brya/var/orisa: Update Type C DisplayPort HPD Configuration
[coreboot2.git] / src / mainboard / google / brya / variants / osiris / overridetree.cb
blob364b7ac7de0f78452b3754e3fa7c1b5be9c65658
1 fw_config
2 field KB_BL 0 0
3 option KB_BL_ABSENT 0
4 option KB_BL_PRESENT 1
5 end
6 field AUDIO 2 3
7 option AUDIO_UNKNOWN 0
8 option MAX98360_NAU88L25B_I2S 1
9 end
10 end
11 chip soc/intel/alderlake
12 register "domain_vr_config[VR_DOMAIN_IA]" = "{
13 .enable_fast_vmode = 1,
14 }"
15
16 register "sagv" = "SaGv_Enabled"
17
18 # As per Intel Advisory doc#723158, the change is required to prevent possible
19 # display flickering issue.
20 register "usb2_phy_sus_pg_disable" = "1"
21
22 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
23 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
24
25 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
26
27 # FIVR configurations are disabled since the board doesn't have V1p05 and Vnn
28 # bypass rails implemented.
29 register "ext_fivr_settings" = "{
30 .configure_ext_fivr = 1,
31 }"
32
33 # Intel Common SoC Config
34 #+-------------------+---------------------------+
35 #| Field | Value |
36 #+-------------------+---------------------------+
37 #| I2C0 | Audio |
38 #| I2C1 | cr50 TPM. Early init is |
39 #| | required to set up a BAR |
40 #| | for TPM communication |
41 #| I2C5 | Trackpad |
42 #+-------------------+---------------------------+
43
44 register "common_soc_config" = "{
45 .i2c[0] = {
46 .speed = I2C_SPEED_FAST,
47 .rise_time_ns = 650,
48 .fall_time_ns = 400,
49 .data_hold_time_ns = 50,
50 },
51 .i2c[1] = {
52 .early_init = 1,
53 .speed = I2C_SPEED_FAST,
54 .rise_time_ns = 600,
55 .fall_time_ns = 400,
56 .data_hold_time_ns = 50,
57 },
58 .i2c[5] = {
59 .speed = I2C_SPEED_FAST,
60 .rise_time_ns = 650,
61 .fall_time_ns = 400,
62 .data_hold_time_ns = 50,
63 },
64 }"
65
66 register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
67 .tdp_pl1_override = 28,
68 .tdp_pl2_override = 55,
69 .tdp_pl4 = 114,
70 }"
71
72 device domain 0 on
73 device ref igpu on
74 chip drivers/gfx/generic
75 register "device_count" = "6"
76 # DDIA for eDP
77 register "device[0].name" = ""LCD0""
78 # Internal panel on the first port of the graphics chip
79 register "device[0].type" = "panel"
80 # DDIB for HDMI
81 register "device[1].name" = ""DD01""
82 # TCP0 (DP-1) for port C0
83 register "device[2].name" = ""DD02""
84 register "device[2].use_pld" = "true"
85 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
86 # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
87 register "device[3].name" = ""DD03""
88 # TCP2 (DP-3) for port C1
89 register "device[4].name" = ""DD04""
90 register "device[4].use_pld" = "true"
91 register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
92 # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
93 register "device[5].name" = ""DD05""
94 device generic 0 on end
95 end
96 end # Integrated Graphics Device
97 device ref dtt on
98 chip drivers/intel/dptf
99 ## sensor information
100 register "options.tsr[0].desc" = ""DRAM""
101 register "options.tsr[1].desc" = ""Soc""
102 register "options.tsr[2].desc" = ""Charger""
103
104 # TODO: below values are initial reference values only
105 ## Active Policy
106 register "policies.active" = "{
107 [0] = {
108 .target = DPTF_CPU,
109 .thresholds = {
110 TEMP_PCT(85, 90),
111 TEMP_PCT(75, 80),
112 TEMP_PCT(68, 70),
113 TEMP_PCT(62, 60),
114 TEMP_PCT(55, 50),
115 TEMP_PCT(50, 40),
116 TEMP_PCT(40, 30),
117 }
118 },
119 [1] = {
120 .target = DPTF_TEMP_SENSOR_1,
121 .thresholds = {
122 TEMP_PCT(60, 90),
123 TEMP_PCT(55, 80),
124 TEMP_PCT(52, 70),
125 TEMP_PCT(48, 60),
126 TEMP_PCT(44, 50),
127 TEMP_PCT(40, 40),
128 TEMP_PCT(36, 30),
129 }
130 }
131 }"
132
133 ## Passive Policy
134 register "policies.passive" = "{
135 [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
136 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
137 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
138 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
139 }"
140
141 ## Critical Policy
142 register "policies.critical" = "{
143 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
144 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
145 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
146 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
147 }"
148
149 register "controls.power_limits" = "{
150 .pl1 = {
151 .min_power = 18000,
152 .max_power = 20000,
153 .time_window_min = 28 * MSECS_PER_SEC,
154 .time_window_max = 32 * MSECS_PER_SEC,
155 .granularity = 200,
156 },
157 .pl2 = {
158 .min_power = 43000,
159 .max_power = 43000,
160 .time_window_min = 28 * MSECS_PER_SEC,
161 .time_window_max = 32 * MSECS_PER_SEC,
162 .granularity = 1000,
163 }
164 }"
165
166 ## Charger Performance Control (Control, mA)
167 register "controls.charger_perf" = "{
168 [0] = { 255, 1700 },
169 [1] = { 24, 1500 },
170 [2] = { 16, 1000 },
171 [3] = { 8, 500 }
172 }"
173
174 ## Fan Performance Control (Percent, Speed, Noise, Power)
175 register "controls.fan_perf" = "{
176 [0] = { 90, 6700, 220, 2200, },
177 [1] = { 80, 5800, 180, 1800, },
178 [2] = { 70, 5000, 145, 1450, },
179 [3] = { 60, 4900, 115, 1150, },
180 [4] = { 50, 3838, 90, 900, },
181 [5] = { 40, 2904, 55, 550, },
182 [6] = { 30, 2337, 30, 300, },
183 [7] = { 20, 1608, 15, 150, },
184 [8] = { 10, 800, 10, 100, },
185 [9] = { 0, 0, 0, 50, }
186 }"
187
188 ## Fan options
189 register "options.fan.fine_grained_control" = "1"
190 register "options.fan.step_size" = "2"
191
192 device generic 0 alias dptf_policy on end
193 end
194 end
195 device ref tbt_pcie_rp0 off end
196 device ref tbt_pcie_rp1 off end
197 device ref tbt_pcie_rp2 off end
198 device ref tcss_dma0 off end
199 device ref tcss_dma1 off end
200 device ref pcie4_0 on
201 # Enable CPU PCIE RP 1 using CLK 0
202 register "cpu_pcie_rp[CPU_RP(1)]" = "{
203 .clk_req = 0,
204 .clk_src = 0,
205 .flags = PCIE_RP_LTR | PCIE_RP_AER,
206 }"
207 end
208 device ref cnvi_wifi on
209 chip drivers/wifi/generic
210 register "wake" = "GPE0_PME_B0"
211 device generic 0 on end
212 end
213 end
214 device ref i2c0 on
215 chip drivers/i2c/nau8825
216 register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
217 register "jkdet_enable" = "1"
218 register "jkdet_pull_enable" = "0"
219 register "jkdet_pull_up" = "0"
220 register "jkdet_polarity" = "1" # ActiveLow
221 register "vref_impedance" = "2" # 125kOhm
222 register "micbias_voltage" = "6" # 2.754
223 register "sar_threshold_num" = "4"
224 register "sar_threshold[0]" = "0x0C"
225 register "sar_threshold[1]" = "0x1C"
226 register "sar_threshold[2]" = "0x38"
227 register "sar_threshold[3]" = "0x60"
228 register "sar_hysteresis" = "1"
229 register "sar_voltage" = "0" # VDDA
230 register "sar_compare_time" = "0" # 500ns
231 register "sar_sampling_time" = "0" # 2us
232 register "short_key_debounce" = "2" # 100ms
233 register "jack_insert_debounce" = "7" # 512ms
234 register "jack_eject_debounce" = "7" # 512ms
235 device i2c 1a on
236 probe AUDIO MAX98360_NAU88L25B_I2S
237 end
238 end
239 end #I2C0
240 device ref i2c1 on
241 chip drivers/i2c/tpm
242 register "hid" = ""GOOG0005""
243 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
244 device i2c 50 on end
245 end
246 end
247 device ref i2c5 on
248 chip drivers/i2c/generic
249 register "hid" = ""ELAN0000""
250 register "desc" = ""ELAN Touchpad""
251 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
252 register "wake" = "GPE0_DW2_14"
253 register "detect" = "1"
254 device i2c 15 on end
255 end
256 chip drivers/i2c/hid
257 register "generic.hid" = ""SYNA0000""
258 register "generic.cid" = ""ACPI0C50""
259 register "generic.desc" = ""Synaptics Touchpad""
260 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
261 register "generic.wake" = "GPE0_DW2_14"
262 register "generic.detect" = "1"
263 register "hid_desc_reg_offset" = "0x20"
264 device i2c 0x2c on end
265 end
266 end
267 device ref hda on
268 chip drivers/generic/max98357a
269 register "hid" = ""MX98360A""
270 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
271 register "sdmode_delay" = "5"
272 device generic 0 on
273 probe AUDIO MAX98360_NAU88L25B_I2S
274 end
275 end
276 chip drivers/sof
277 register "spkr_tplg" = "max98360a"
278 register "jack_tplg" = "nau8825"
279 register "mic_tplg" = "_2ch_pdm0"
280 device generic 0 on end
281 end
282 end
283 device ref pcie_rp6 off end # PCIE6 WWAN
284 device ref pcie_rp7 on
285 chip drivers/net
286 register "wake" = "GPE0_DW0_07"
287 register "led_feature" = "0xe0"
288 register "customized_led0" = "0x23f"
289 register "customized_led2" = "0x028"
290 register "enable_aspm_l1_2" = "1"
291 register "add_acpi_dma_property" = "true"
292 device pci 00.0 on end
293 end
294 # Enable PCIE 7 using clk 6
295 register "pch_pcie_rp[PCH_RP(7)]" = "{
296 .clk_src = 6,
297 .clk_req = 6,
298 .flags = PCIE_RP_LTR | PCIE_RP_AER,
299 }"
300 end # RTL8125 Ethernet NIC
301 device ref pcie_rp8 off end # PCIE8 SD card
302 device ref pcie_rp9 off end # PCIE9-12 SSD
303 device ref gspi1 off end
304 device ref pch_espi on
305 chip ec/google/chromeec
306 use conn0 as mux_conn[0]
307 use conn1 as mux_conn[1]
308 device pnp 0c09.0 on end
309 end
310 end
311 device ref pmc hidden
312 chip drivers/intel/pmc_mux
313 device generic 0 on
314 chip drivers/intel/pmc_mux/conn
315 use usb2_port1 as usb2_port
316 use tcss_usb3_port1 as usb3_port
317 device generic 0 alias conn0 on end
318 end
319 chip drivers/intel/pmc_mux/conn
320 use usb2_port3 as usb2_port
321 use tcss_usb3_port3 as usb3_port
322 device generic 1 alias conn1 on end
323 end
324 end
325 end
326 end
327 device ref tcss_xhci on
328 chip drivers/usb/acpi
329 device ref tcss_root_hub on
330 chip drivers/usb/acpi
331 register "desc" = ""USB3 Type-C Port C0 (MLB)""
332 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
333 register "use_custom_pld" = "true"
334 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
335 register "usb_lpm_incapable" = "true"
336 device ref tcss_usb3_port1 on end
337 end
338 chip drivers/usb/acpi
339 register "desc" = ""USB3 Type-C Port C1 (MLB)""
340 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
341 register "use_custom_pld" = "true"
342 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
343 register "usb_lpm_incapable" = "true"
344 device ref tcss_usb3_port3 on end
345 end
346 end
347 end
348 end
349 device ref xhci on
350 chip drivers/usb/acpi
351 device ref xhci_root_hub on
352 chip drivers/usb/acpi
353 register "desc" = ""USB2 Type-C Port C0 (MLB)""
354 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
355 register "use_custom_pld" = "true"
356 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
357 device ref usb2_port1 on end
358 end
359 chip drivers/usb/acpi
360 register "desc" = ""USB2 Type-C Port C1 (MLB)""
361 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
362 register "use_custom_pld" = "true"
363 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
364 device ref usb2_port3 on end
365 end
366 chip drivers/usb/acpi
367 register "desc" = ""USB2 Camera""
368 register "type" = "UPC_TYPE_INTERNAL"
369 device ref usb2_port6 on end
370 end
371 chip drivers/usb/acpi
372 register "desc" = ""USB2 Type-A Port A0 (MLB)""
373 register "type" = "UPC_TYPE_A"
374 register "use_custom_pld" = "true"
375 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))"
376 device ref usb2_port9 on end
377 end
378 chip drivers/usb/acpi
379 register "desc" = ""USB2 Bluetooth""
380 register "type" = "UPC_TYPE_INTERNAL"
381 register "reset_gpio" =
382 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
383 device ref usb2_port10 on end
384 end
385 chip drivers/usb/acpi
386 register "desc" = ""USB3 Type-A Port A0 (MLB)""
387 register "type" = "UPC_TYPE_USB3_A"
388 register "use_custom_pld" = "true"
389 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))"
390 device ref usb3_port1 on end
391 end
392 end
393 end
394 end
395 end
396 end
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