src/mainboard/google/brya/variants/trulo/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <soc/gpio.h>
   6 #include <types.h>
   7 #include <vendorcode/google/chromeos/chromeos.h>
   8
   9 /* Pad configuration in ramstage */
  10 static const struct pad_config gpio_table[] = {
  11         /* A0 thru A4, A9 and A10 come configured out of reset, do not touch */
  12         /* A0  : ESPI_IO0 ==> ESPI_SOC_D0_EC */
  13         /* A1  : ESPI_IO1 ==> ESPI_SOC_D1_EC */
  14         /* A2  : ESPI_IO2 ==> ESPI_SOC_D2_EC */
  15         /* A3  : ESPI_IO3 ==> ESPI_SOC_D3_EC */
  16         /* A4  : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */
  17         /* A5  : ESPI_ALERT0# ==> NC */
  18         PAD_NC(GPP_A5, NONE),
  19         /* A6  : ESPI_ALERT1# ==> NC */
  20         PAD_NC(GPP_A6, NONE),
  21         /* A7  : NC */
  22         PAD_NC(GPP_A7, NONE),
  23         /* A8  : NC */
  24         PAD_NC(GPP_A8, NONE),
  25         /* A9  : ESPI_CLK ==> ESPI_SOC_CLK */
  26         /* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
  27         /* A11 : EN_SPK_PA ==> NC */
  28         PAD_NC(GPP_A11, NONE),
  29         /* A12 : NC */
  30         PAD_NC(GPP_A12, NONE),
  31         /* A13 : GPP_A13 ==> SOC_BT_ON */
  32         PAD_CFG_GPO_LOCK(GPP_A13, 1, LOCK_CONFIG),
  33         /* A14 : USB_OC1# ==> NC */
  34         PAD_NC(GPP_A14, NONE),
  35         /* A15 : USB_OC2# ==> NC */
  36         PAD_NC(GPP_A15, NONE),
  37         /* A16 : USB_OC3# ==> NC */
  38         PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
  39         /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */
  40         PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
  41         /* A18 : DDSP_HPDB ==> DDI2_HPD */
  42         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  43         /* A19 : NC */
  44         PAD_NC(GPP_A19, NONE),
  45         /* A20 : NC */
  46         PAD_NC(GPP_A20, NONE),
  47         /* A21 : DDPC_CTRLCLK ==> TCHSCR_REPORT_EN */
  48         PAD_CFG_GPO(GPP_A21, 0, DEEP),
  49         /* A22 : GPP_A22 ==> TPM_PIRQ# */
  50         PAD_CFG_GPI(GPP_A22, NONE, DEEP),
  51         /* A23 : GPP_A23 ==> NC */
  52         PAD_NC(GPP_A23, NONE),
  53
  54         /* B0  : CORE_VID0 ==> VCCIN_AUX_VID0 */
  55         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  56         /* B1  : CORE_VID1 ==> VCCIN_AUX_VID1 */
  57         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  58         /* B2  : NC */
  59         PAD_NC(GPP_B2, NONE),
  60         /* B3  : CPU_GP2 ==> EC_TP_INT */
  61         PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT),
  62         /* B4  : PROC_GP3 ==> EN_PP3300_UCAM_X */
  63         PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
  64         /* B5  : GPP_B5 ==> ISH_I2C0_SCL */
  65         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
  66         /* B6  : GPP_B6 ==> ISH_I2C0_SDA */
  67         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
  68         /* B7  : GPP_B7 ==> NC */
  69         PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
  70         /* B8  : GPP_B8 ==> NC */
  71         PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG),
  72         /* B9  : Not available */
  73         PAD_NC(GPP_B9, NONE),
  74         /* B10 : Not available */
  75         PAD_NC(GPP_B10, NONE),
  76         /* B11 : SOC_PD_INT# */
  77         PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
  78         /* B12 : SLP_S0# ==> PM_SLP_S0# */
  79         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  80         /* B13 : PLTRST# ==> PLT_RST_L */
  81         PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG),
  82         /* B14 : SPKR ==> GPP_B14_STRAP */
  83         PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG),
  84         /* B15 : NC */
  85         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  86         /* B16  : GPP_B16 ==> I2C_5_SDA */
  87         PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
  88         /* B17  : GPP_B17 ==> I2C_5_SCL */
  89         PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
  90         /* B18 : GPP_B18 ==> GPP_B18_STRAP */
  91         PAD_NC(GPP_B18, NONE),
  92         /* B19 : Not available */
  93         PAD_NC(GPP_B19, NONE),
  94         /* B20 : Not available */
  95         PAD_NC(GPP_B20, NONE),
  96         /* B21 : Not available */
  97         PAD_NC(GPP_B21, NONE),
  98         /* B22 : Not available */
  99         PAD_NC(GPP_B22, NONE),
 100         /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
 101         PAD_NC(GPP_B23, NONE),
 102
 103         /* C0  : NC */
 104         PAD_NC(GPP_C0, NONE),
 105         /* C1  : NC */
 106         PAD_NC(GPP_C1, NONE),
 107         /* C2  : SMBALERT# ==> GPP_C2_STRAP */
 108         PAD_NC(GPP_C2, NONE),
 109         /* C3  : NC */
 110         PAD_NC(GPP_C3, NONE),
 111         /* C4  : NC */
 112         PAD_NC(GPP_C4, NONE),
 113         /* C5  : SML0ALERT# ==> GPP_C5_STRAP */
 114         PAD_NC(GPP_C5, NONE),
 115         /* C6  : SML1_SMBCLK */
 116         PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 117         /* C7  : SML1_SMBDATA */
 118         PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
 119
 120         /* D0  : ISH_GP0 ==> SOC_GSEN1_INT# */
 121         PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
 122         /* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
 123         PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
 124         /* D2  : ISH_GP2 ==> SEN_MODE_EC_PCH_INT_ODL */
 125         PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
 126         /* D3  : NC */
 127         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
 128         /* D4  : NC */
 129         PAD_NC(GPP_D4, NONE),
 130         /* D5  : NC */
 131         PAD_NC(GPP_D5, NONE),
 132         /* D6  : NC */
 133         PAD_NC(GPP_D6, NONE),
 134         /* D7  : GPP_D7 ==> CLKREQ_PCIE#2 */
 135         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 136         /* D8  : SRCCLKREQ3# ==> NC */
 137         PAD_NC(GPP_D8, NONE),
 138         /* D9  : NC */
 139         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
 140         /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
 141         PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
 142         /* D11 : NC */
 143         PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
 144         /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
 145         PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
 146         /* D13 : UART0_ISH_RX_DBG_TX */
 147         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
 148         /* D14 : UART0_ISH_TX_DBG_RX */
 149         PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
 150         /* D15  : GPP_D15 ==> SOC_TS_I2C_RST# */
 151         PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
 152         /* D16 : ISH_UART0_CTS# ==> SOC_TS_I2C_INT# */
 153         PAD_CFG_GPI_LOCK(GPP_D16, NONE, LOCK_CONFIG),
 154         /* D17 : NC */
 155         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
 156         /* D18 : NC */
 157         PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
 158         /* D19 : I2S_MCLK1_OUT ==> NC */
 159         PAD_NC(GPP_D19, NONE),
 160
 161         /* E0  : NC */
 162         PAD_NC(GPP_E0, NONE),
 163         /* E1  : THC0_SPI1_IO2 ==> RAM_ID1 */
 164         PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
 165         /* E2  : THC0_SPI1_IO3 ==> RAM_ID0 */
 166         PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
 167         /* E3  : PROC_GP0 ==> SOC_WP_OD */
 168         PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E3, NONE, LOCK_CONFIG),
 169         /* E4  : NC */
 170         PAD_NC(GPP_E4, NONE),
 171         /* E5  : NC */
 172         PAD_NC(GPP_E5, NONE),
 173         /* E6  : THC0_SPI1_RST# ==> GPP_E6_STRAP */
 174         PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
 175         /* E7  : NC */
 176         PAD_NC(GPP_E7, NONE),
 177         /* E8  : GPP_E8 ==> WLAN_DISABLE_L */
 178         PAD_CFG_GPO(GPP_E8, 1, DEEP),
 179         /* E9  : NC */
 180         PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
 181         /* E10 : NC */
 182         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 183         /* E11 : NC */
 184         PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 185         /* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */
 186         PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
 187         /* E13 : NC */
 188         PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 189         /* E14 : DDSP_HPDA ==> EDP_HPD */
 190         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 191         /* E15 : NC */
 192         PAD_NC(GPP_E15, NONE),
 193         /* E16 : NC */
 194         PAD_NC(GPP_E16, NONE),
 195         /* E17  : GPP_E17 ==> SOC_TS_PWR_EN */
 196         PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
 197         /* E18 : NC */
 198         PAD_NC(GPP_E18, NONE),
 199         /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
 200         PAD_NC(GPP_E19, NONE),
 201         /* E20 : NC */
 202         PAD_NC(GPP_E20, NONE),
 203         /* E21 : NC */
 204         PAD_NC(GPP_E21, NONE),
 205         /* E22 : DDPA_CTRLCLK ==> TCP0_DISP_AUX_P_BIAS */
 206         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
 207         /* E23 : DDPA_CTRLDATA ==> TCP0_DISP_AUX_N_BIAS */
 208         PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
 209
 210         /* F0  : CNV_BRI_DT ==> CNV_BRI_CTX_DRX */
 211         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 212         /* F1  : CNV_BRI_RSP ==> CNV_BRI_CRX_DTX */
 213         PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
 214         /* F2  : CNV_RGI_DT ==> CNV_RGI_CTX_DRX */
 215         PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
 216         /* F3  : CNV_RGI_RSP ==> CNV_RGI_CRX_DTX */
 217         PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
 218         /* F4  : CNV_RF_RESET# ==> CNV_RF_RESET# */
 219         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 220         /* F5  : MODEM_CLKREQ ==> CLKREQ_CNV# */
 221         PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
 222         /* F6  : CNV_PA_BLANKING ==> NC */
 223         PAD_NC(GPP_F6, NONE),
 224         /* F7  : GPP_F7 ==> GPP_F7_STRAP */
 225         PAD_NC(GPP_F7, NONE),
 226         /* F8  : Not available */
 227         PAD_NC(GPP_F8, NONE),
 228         /* F9  : Not available */
 229         PAD_NC(GPP_F9, NONE),
 230         /* F10 : GPP_F10 ==> GPP_F10_STRAP */
 231         PAD_NC(GPP_F10, NONE),
 232         /* F11 : NC */
 233         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 234         /* F12 : NC */
 235         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 236         /* F13 : NC */
 237         PAD_NC(GPP_F13, NONE),
 238         /* F14 : NC */
 239         PAD_NC(GPP_F14, NONE),
 240         /* F15 : NC */
 241         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 242         /* F16 : NC */
 243         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 244         /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
 245         PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, EDGE_SINGLE, INVERT),
 246         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 247         PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
 248         /* F19 : Not available */
 249         PAD_NC(GPP_F19, NONE),
 250         /* F20 : Not available */
 251         PAD_NC(GPP_F20, NONE),
 252         /* F21 : Not available */
 253         PAD_NC(GPP_F21, NONE),
 254         /* F22 : NC */
 255         PAD_NC(GPP_F22, NONE),
 256         /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
 257         PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
 258
 259         /* H0  : GPP_H0_STRAP */
 260         PAD_NC(GPP_H0, NONE),
 261         /* H1  : GPP_H1_STRAP */
 262         PAD_NC(GPP_H1, NONE),
 263         /* H2  : GPP_H2_STRAP */
 264         PAD_NC(GPP_H2, NONE),
 265         /* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
 266         PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
 267         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 268         PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
 269         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 270         PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
 271         /* H6 : I2C1_SDA ==> I2C_1_SDA */
 272         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 273         /* H7 : I2C1_SCL ==> I2C_1_SCL */
 274         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 275         /* H8  : NC */
 276         PAD_NC(GPP_H8, NONE),
 277         /* H9  : NC */
 278         PAD_NC(GPP_H9, NONE),
 279         /* H10 : UART0_RXD ==> UART_2_CRXD_DTXD */
 280         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 281         /* H11 : UART0_TXD ==> UART_2_CTXD_DRXD */
 282         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 283         /* H12 : GPP_H12 ==> ISH_GP6B */
 284         PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
 285         /* H13 : GPP_H13 ==> ISH_GP7B */
 286         PAD_CFG_NF(GPP_H13, NONE, DEEP, NF4),
 287         /* H14 : Not available */
 288         PAD_NC(GPP_H14, NONE),
 289         /* H15  : DDPB_CTRLCLK ==> SOC_DP2_CTRL_CLK */
 290         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 291         /* H16 : Not available */
 292         PAD_NC(GPP_H16, NONE),
 293         /* H17  : DDPB_CTRLDATA ==> SOC_DP2_CTRL_DATA */
 294         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 295         /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */
 296         PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 297         /* H19 : NC */
 298         PAD_NC(GPP_H19, NONE),
 299         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 300         PAD_CFG_GPO(GPP_H20, 1, DEEP),
 301         /* H21 : NC */
 302         PAD_NC(GPP_H21, NONE),
 303         /* H22 : NC */
 304         PAD_NC(GPP_H22, NONE),
 305         /* H23 : NC */
 306         PAD_NC(GPP_H23, NONE),
 307
 308         /* R0  : HDA_BCLK ==> HDA_BIT_CLK */
 309         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
 310         /* R1  : HDA_SYNC ==> HDA_SYNC */
 311         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
 312         /* R2 : HDA_SDO ==> HDA_SDOUT */
 313         PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
 314         /* R3 : HDA_SDI0 ==> HDA_SDIN0 */
 315         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
 316         /* R4 : HDA_RST# ==> HDA_RST# */
 317         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
 318         /* R5 : HDA_SDI1 ==> HDA_SDIN1 */
 319         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
 320         /* R6  : DMIC_CLK_A_1A ==> NC */
 321         PAD_NC(GPP_R6, NONE),
 322         /* R7  : DMIC_DATA_1A ==> NC */
 323         PAD_NC(GPP_R7, NONE),
 324
 325         /* S0  : I2S_SPK_BCLK_R ==> NC */
 326         PAD_NC(GPP_S0, NONE),
 327         /* S1  : I2S_SPK_LRCK_R ==> NC */
 328         PAD_NC(GPP_S1, NONE),
 329         /* S2 : DMIC_CKL_A0 ==> PCH_DMIC_CLK */
 330         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
 331         /* S3 : DMIC_DATA0 ==> PCH_DMIC_DATA */
 332         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
 333         /* S4  : NC */
 334         PAD_NC(GPP_S4, NONE),
 335         /* S5  : NC */
 336         PAD_NC(GPP_S5, NONE),
 337         /* S6  : NC */
 338         PAD_NC(GPP_S6, NONE),
 339         /* S7  : NC */
 340         PAD_NC(GPP_S7, NONE),
 341
 342         /* I5  : NC */
 343         PAD_NC(GPP_I5, NONE),
 344         /* I7  : EMMC_CMD ==> EMMC_CMD */
 345         PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
 346         /* I8  : EMMC_DATA0 ==> EMMC_D0 */
 347         PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
 348         /* I9  : EMMC_DATA1 ==> EMMC_D1 */
 349         PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
 350         /* I10 : EMMC_DATA2 ==> EMMC_D2 */
 351         PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
 352         /* I11 : EMMC_DATA3 ==> EMMC_D3 */
 353         PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
 354         /* I12 : EMMC_DATA4 ==> EMMC_D4 */
 355         PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
 356         /* I13 : EMMC_DATA5 ==> EMMC_D5 */
 357         PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
 358         /* I14 : EMMC_DATA6 ==> EMMC_D6 */
 359         PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
 360         /* I15 : EMMC_DATA7 ==> EMMC_D7 */
 361         PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
 362         /* I16 : EMMC_RCLK ==> EMMC_RCLK */
 363         PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
 364         /* I17 : EMMC_CLK ==> EMMC_CLK */
 365         PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
 366         /* I18 : EMMC_RESET# ==> EMMC_RST_L */
 367         PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
 368
 369         /* GPD0  : BATLOW# ==> SOC_BATLOW_L */
 370         PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 371         /* GPD1  : ACPRESENT ==> SOC_ACPRESENT */
 372         PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 373         /* GPD2  : EC_SOC_INT_ODL */
 374         PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT),
 375         /* GPD3  : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */
 376         PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
 377         /* GPD4  : SLP_S3# ==> SLP_S3_L */
 378         PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 379         /* GPD5  : SLP_S4# ==> SLP_S4_L */
 380         PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 381         /* GPD6  : SLP_A# ==> NC */
 382         PAD_NC(GPD6, NONE),
 383         /* GPD7  : GPD7_STRAP */
 384         PAD_NC(GPD7, NONE),
 385         /* GPD8  : SUSCLK ==> PCH_SUSCLK */
 386         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 387         /* GPD9  : NC */
 388         PAD_NC(GPD9, NONE),
 389         /* GPD10 : SLP_S5# ==> NC */
 390         PAD_NC(GPD10, NONE),
 391         /* GPD11 : NC */
 392         PAD_NC(GPD11, NONE),
 393
 394         /* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */
 395         /* vCNV_BT_UART_TXD */
 396         PAD_NC(GPP_VGPIO_6, NONE),
 397         /* vCNV_BT_UART_RXD */
 398         PAD_NC(GPP_VGPIO_7, NONE),
 399         /* vCNV_BT_UART_CTS_B */
 400         PAD_NC(GPP_VGPIO_8, NONE),
 401         /* vCNV_BT_UART_RTS_B */
 402         PAD_NC(GPP_VGPIO_9, NONE),
 403
 404         /* Configure the unused vUART for Bluetooth pads to NC mode. */
 405         /* vUART0_TXD */
 406         PAD_NC(GPP_VGPIO_18, NONE),
 407         /* vUART0_RXD */
 408         PAD_NC(GPP_VGPIO_19, NONE),
 409         /* vUART0_CTS_B */
 410         PAD_NC(GPP_VGPIO_20, NONE),
 411         /* vUART0_RTS_B */
 412         PAD_NC(GPP_VGPIO_21, NONE),
 413 };
 414
 415 /* Early pad configuration in bootblock */
 416 static const struct pad_config early_gpio_table[] = {
 417         /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */
 418         PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
 419         /* E3 : PROC_GP0 ==> SOC_WP_OD */
 420         PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
 421         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 422         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 423         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 424         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 425         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 426         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 427         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 428         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 429         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 430         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 431 };
 432
 433 /* Fill romstage gpio configuration */
 434 static const struct pad_config romstage_gpio_table[] = {
 435         /* Enable touchscreen, hold in reset */
 436         /* E17  : GPP_E17 ==> SOC_TS_PWR_EN */
 437         PAD_CFG_GPO(GPP_E17, 1, DEEP),
 438         /* D15  : GPP_D15 ==> SOC_TS_I2C_RST# */
 439         PAD_CFG_GPO(GPP_D15, 0, DEEP),
 440 };
 441
 442 const struct pad_config *variant_gpio_table(size_t *num)
 443 {
 444         *num = ARRAY_SIZE(gpio_table);
 445         return gpio_table;
 446 }
 447
 448 const struct pad_config *variant_gpio_override_table(size_t *num)
 449 {
 450         *num = 0;
 451         return NULL;
 452 }
 453
 454 const struct pad_config *variant_early_gpio_table(size_t *num)
 455 {
 456         *num = ARRAY_SIZE(early_gpio_table);
 457         return early_gpio_table;
 458 }
 459
 460 static const struct cros_gpio cros_gpios[] = {
 461         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 462         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 463 };
 464 DECLARE_CROS_GPIOS(cros_gpios);
 465
 466 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 467 {
 468         *num = ARRAY_SIZE(romstage_gpio_table);
 469         return romstage_gpio_table;
 470 }