src/mainboard/google/brya/variants/yaviks/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7 #include <fw_config.h>
   8
   9 /* Pad configuration in ramstage */
  10 static const struct pad_config override_gpio_table[] = {
  11         /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
  12         PAD_CFG_GPO(GPP_A21, 0, DEEP),
  13         /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
  14         PAD_CFG_GPO(GPP_A22, 1, DEEP),
  15
  16         /* B5  : SOC_I2C_SUB_SDA ==> NC */
  17         PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
  18         /* B6  : SOC_I2C_SUB_SCL ==> NC */
  19         PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
  20
  21         /* D3  : WCAM_RST_L ==> NC */
  22         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  23         /* D15 : EN_PP2800_WCAM_X ==> NC */
  24         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  25         /* D16 : EN_PP1800_PP1200_WCAM_X ==> NC */
  26         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  27         /* D17 : NC ==> SD_WAKE_N */
  28         PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  29
  30         /* E20 : DDP2_CTRLCLK ==> NC  */
  31         PAD_NC(GPP_E20, NONE),
  32         /* E21 : DDP2_CTRLDATA ==> NC */
  33         PAD_NC(GPP_E21, NONE),
  34
  35         /* F6  : CNV_PA_BLANKING ==> NC */
  36         PAD_NC(GPP_F6, NONE),
  37         /* F12 : GSXDOUT ==> NC */
  38         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  39         /* F13 : GSXSLOAD ==> NC */
  40         PAD_NC(GPP_F13, NONE),
  41         /* F15 : GSXSRESET# ==> NC */
  42         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  43         /* F23 : V1P05EXT_CTRL ==> NC */
  44         PAD_NC(GPP_F23, NONE),
  45
  46         /* H8  : CNV_MFUART2_RXD ==> NC */
  47         PAD_NC(GPP_H8, NONE),
  48         /* H9  : CNV_MFUART2_TXD ==> NC */
  49         PAD_NC(GPP_H9, NONE),
  50         /* H19 : SRCCLKREQ4# ==> NC */
  51         PAD_NC(GPP_H19, NONE),
  52         /* H22 : IMGCLKOUT3 ==> NC */
  53         PAD_NC(GPP_H22, NONE),
  54         /* H23 : GPP_H23 ==> NC */
  55         PAD_NC(GPP_H23, NONE),
  56
  57         /* R6 : DMIC_CLK_A_1A ==> NC */
  58         PAD_NC(GPP_R6, NONE),
  59         /* R7 : DMIC_DATA_1A ==> NC */
  60         PAD_NC(GPP_R7, NONE),
  61 };
  62
  63 /* Pad configuration in ramstage for yavilla */
  64 static const struct pad_config override_gpio_table_yavilla[] = {
  65         /* A8  : WWAN_RF_DISABLE_ODL */
  66         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  67         /* A18 : NC ==> HDMI_HPD_SRC */
  68         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  69         /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
  70         PAD_CFG_GPO(GPP_A21, 0, DEEP),
  71         /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
  72         PAD_CFG_GPO(GPP_A22, 1, DEEP),
  73
  74         /* D6  : WWAN_EN */
  75         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  76         /* D8  : SD_CLKREQ_ODL ==> NC  */
  77         PAD_NC(GPP_D8, NONE),
  78
  79         /* F6  : CNV_PA_BLANKING ==> NC */
  80         PAD_NC(GPP_F6, NONE),
  81         /* F12 : WWAN_RST_ODL */
  82         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  83         /* F23 : V1P05EXT_CTRL ==> NC */
  84         PAD_NC(GPP_F23, NONE),
  85
  86         /* H8  : CNV_MFUART2_RXD ==> NC */
  87         PAD_NC(GPP_H8, NONE),
  88         /* H9  : CNV_MFUART2_TXD ==> NC */
  89         PAD_NC(GPP_H9, NONE),
  90         /* H12 : SD_PERST_L ==> NC */
  91         PAD_NC(GPP_H12, NONE),
  92         /* H13 : EN_PP3300_SD_X ==> NC */
  93         PAD_NC(GPP_H13, NONE),
  94         /* H15 : HDMI_SRC_SCL */
  95         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
  96         /* H17 : HDMI_SRC_SDA */
  97         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
  98         /* H19 : SRCCLKREQ4# ==> NC */
  99         PAD_NC(GPP_H19, NONE),
 100         /* H23 : WWAN_SAR_DETECT_ODL */
 101         PAD_CFG_GPO(GPP_H23, 1, DEEP),
 102 };
 103
 104 /* Early pad configuration in bootblock */
 105 static const struct pad_config early_gpio_table[] = {
 106         /* H12 : UART0_RTS# ==> SD_PERST_L */
 107         PAD_CFG_GPO(GPP_H12, 0, DEEP),
 108         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 109         PAD_CFG_GPO(GPP_H20, 0, DEEP),
 110         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 111         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 112         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 113         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 114         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 115         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 116         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 117         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 118         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 119         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 120         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 121         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 122         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 123         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 124         /* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
 125         PAD_CFG_GPO(GPP_B11, 1, DEEP),
 126         /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
 127         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 128 };
 129
 130 /* Early pad configuration in bootblock for yavilla */
 131 static const struct pad_config early_gpio_table_yavilla[] = {
 132         /* D6  : WWAN_EN */
 133         PAD_CFG_GPO(GPP_D6, 0, DEEP),
 134         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 135         PAD_CFG_GPO(GPP_H20, 0, DEEP),
 136         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 137         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 138         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 139         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 140         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 141         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 142         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 143         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 144         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 145         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 146         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 147         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 148         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 149         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 150         /* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
 151         PAD_CFG_GPO(GPP_B11, 1, DEEP),
 152         /* F12 : WWAN_RST_ODL */
 153         PAD_CFG_GPO(GPP_F12, 0, DEEP),
 154 };
 155
 156 static const struct pad_config romstage_gpio_table[] = {
 157         /* Enable touchscreen, hold in reset */
 158         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 159         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 160         /* C1  : SMBDATA ==> USI_RST_L */
 161         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 162
 163         /* H12 : UART0_RTS# ==> SD_PERST_L */
 164         PAD_CFG_GPO(GPP_H12, 1, DEEP),
 165         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 166         PAD_CFG_GPO(GPP_H20, 1, DEEP),
 167 };
 168
 169 static const struct pad_config romstage_gpio_table_yavilla[] = {
 170         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 171         PAD_CFG_GPO(GPP_H20, 1, DEEP),
 172 };
 173
 174 const struct pad_config *variant_gpio_override_table(size_t *num)
 175 {
 176         if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
 177                 *num = ARRAY_SIZE(override_gpio_table_yavilla);
 178                 return override_gpio_table_yavilla;
 179         }
 180         *num = ARRAY_SIZE(override_gpio_table);
 181         return override_gpio_table;
 182 }
 183
 184 const struct pad_config *variant_early_gpio_table(size_t *num)
 185 {
 186         if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
 187                 *num = ARRAY_SIZE(early_gpio_table_yavilla);
 188                 return early_gpio_table_yavilla;
 189         }
 190         *num = ARRAY_SIZE(early_gpio_table);
 191         return early_gpio_table;
 192 }
 193
 194 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 195 {
 196         if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C)) || fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
 197                 *num = ARRAY_SIZE(romstage_gpio_table_yavilla);
 198                 return romstage_gpio_table_yavilla;
 199         }
 200         *num = ARRAY_SIZE(romstage_gpio_table);
 201         return romstage_gpio_table;
 202 }