src/soc/amd/cezanne/Makefile.mk

   1 # SPDX-License-Identifier: BSD-3-Clause
   2
   3 ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
   4
   5 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
   6
   7 # Beware that all-y also adds the compilation unit to verstage on PSP
   8 all-y           += aoac.c
   9 all-y           += config.c
  10 all-y           += i2c.c
  11
  12 # all_x86-y adds the compilation unit to all stages that run on the x86 cores
  13 all_x86-y       += gpio.c
  14 all_x86-y       += uart.c
  15
  16 bootblock-y     += early_fch.c
  17 bootblock-y     += espi_util.c
  18
  19 romstage-y      += fsp_m_params.c
  20
  21 ramstage-y      += acpi.c
  22 ramstage-y      += chip.c
  23 ramstage-y      += cpu.c
  24 ramstage-y      += fch.c
  25 ramstage-y      += fsp_s_params.c
  26 ramstage-y      += graphics.c
  27 ramstage-y      += mca.c
  28 ramstage-y      += memmap.c
  29 ramstage-y      += root_complex.c
  30 ramstage-y      += xhci.c
  31
  32 smm-y           += gpio.c
  33 smm-y           += root_complex.c
  34 smm-y           += smihandler.c
  35 smm-$(CONFIG_DEBUG_SMI) += uart.c
  36
  37 CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
  38 CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi
  39 CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
  40 CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
  41
  42 # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
  43 # Building the cbfs image will fail if the offset isn't large enough
  44 AMD_FW_AB_POSITION := 0x40
  45
  46 CEZANNE_FW_A_POSITION=$(call int-add, \
  47         $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION))
  48
  49 CEZANNE_FW_B_POSITION=$(call int-add, \
  50         $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION))
  51 #
  52 # PSP Directory Table items
  53 #
  54 # Certain ordering requirements apply, however these are ensured by amdfwtool.
  55 # For more information see "AMD Platform Security Processor BIOS Architecture
  56 # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only).
  57 #
  58
  59
  60 ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
  61 PSP_SOFTFUSE_BITS += 7
  62 endif
  63
  64 ifeq ($(CONFIG_PSP_INIT_ESPI),y)
  65 PSP_SOFTFUSE_BITS += 15
  66 endif
  67
  68 ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
  69 # Enable secure debug unlock
  70 PSP_SOFTFUSE_BITS += 0
  71 OPT_TOKEN_UNLOCK="--token-unlock"
  72 endif
  73
  74 ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y)
  75 OPT_PSP_LOAD_MP2_FW="--load-mp2-fw"
  76 else
  77 # Disable MP2 firmware loading
  78 PSP_SOFTFUSE_BITS += 29
  79 endif
  80
  81 ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y)
  82 PSP_SOFTFUSE_BITS += 58
  83 endif
  84
  85 # Use additional Soft Fuse bits specified in Kconfig
  86 PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS))
  87
  88 # type = 0x04
  89 # The flashmap section used for this is expected to be named PSP_NVRAM
  90 PSP_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_START)
  91 PSP_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_SIZE)
  92
  93 # type = 0x3a
  94 ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
  95 PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
  96 endif
  97
  98 # type = 0x54
  99 # The flashmap section used for this is expected to be named PSP_RPMC_NVRAM
 100 PSP_RPMC_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_RPMC_NVRAM_START)
 101 PSP_RPMC_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_RPMC_NVRAM_SIZE)
 102
 103 # type = 0x55
 104 SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE)
 105
 106 #
 107 # BIOS Directory Table items - proper ordering is managed by amdfwtool
 108 #
 109
 110 # type = 0x60
 111 PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY)
 112
 113 # type = 0x61
 114 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
 115
 116 # type = 0x62
 117 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
 118 PSP_ELF_FILE=$(objcbfs)/bootblock.elf
 119 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
 120 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
 121
 122 ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y)
 123 # type = 0x63 - construct APOB NV base/size from flash map
 124 # The flashmap section used for this is expected to be named RW_MRC_CACHE
 125 APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
 126 APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START)
 127 endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE
 128
 129 ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
 130 # type = 0x6B - PSP Shared memory location
 131 ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0)
 132 PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE)
 133 PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map)
 134 endif
 135
 136 # type = 0x52 - PSP Bootloader Userspace Application (verstage)
 137 PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
 138 PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN))
 139 endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK
 140
 141 # Helper function to return a value with given bit set
 142 # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions.
 143 set-bit=$(call int-shift-left, 1 $(call _toint,$1))
 144 PSP_SOFTFUSE=$(shell A=$(call int-add, \
 145                 $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A)
 146
 147 #
 148 # Build the arguments to amdfwtool (order is unimportant).  Missing file names
 149 # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool.
 150 #
 151
 152 add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
 153
 154 OPT_PSP_NVRAM_BASE=$(call add_opt_prefix, $(PSP_NVRAM_BASE), --nvram-base)
 155 OPT_PSP_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_NVRAM_SIZE), --nvram-size)
 156
 157 OPT_PSP_RPMC_NVRAM_BASE=$(call add_opt_prefix, $(PSP_RPMC_NVRAM_BASE), --rpmc-nvram-base)
 158 OPT_PSP_RPMC_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_RPMC_NVRAM_SIZE), --rpmc-nvram-size)
 159
 160 OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage)
 161 OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig)
 162
 163 OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
 164                     $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
 165                     $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
 166
 167 OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
 168 OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
 169 OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
 170 OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
 171
 172 OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem)
 173 OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size)
 174 OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size)
 175 OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base)
 176 OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
 177 OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
 178 OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
 179
 180 OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
 181
 182 OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
 183 OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
 184
 185 OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_RECOVERY_AB), --recovery-ab)
 186
 187 AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 188                 $(OPT_PSP_NVRAM_BASE) \
 189                 $(OPT_PSP_NVRAM_SIZE) \
 190                 $(OPT_PSP_RPMC_NVRAM_BASE) \
 191                 $(OPT_PSP_RPMC_NVRAM_SIZE) \
 192                 $(OPT_APOB_ADDR) \
 193                 $(OPT_DEBUG_AMDFWTOOL) \
 194                 $(OPT_PSP_BIOSBIN_FILE) \
 195                 $(OPT_PSP_BIOSBIN_DEST) \
 196                 $(OPT_PSP_BIOSBIN_SIZE) \
 197                 $(OPT_PSP_SOFTFUSE) \
 198                 $(OPT_PSP_LOAD_MP2_FW) \
 199                 --use-pspsecureos \
 200                 --load-s0i3 \
 201                 $(OPT_TOKEN_UNLOCK) \
 202                 $(OPT_WHITELIST_FILE) \
 203                 $(OPT_SPL_TABLE_FILE) \
 204                 $(OPT_PSP_SHAREDMEM_BASE) \
 205                 $(OPT_PSP_SHAREDMEM_SIZE) \
 206                 $(OPT_EFS_SPI_READ_MODE) \
 207                 $(OPT_EFS_SPI_SPEED) \
 208                 $(OPT_EFS_SPI_MICRON_FLAG) \
 209                 $(OPT_RECOVERY_AB) \
 210                 --config $(CONFIG_AMDFW_CONFIG_FILE) \
 211                 --flashsize $(CONFIG_ROM_SIZE)
 212
 213 $(obj)/amdfw.rom:       $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 214                         $(PSP_VERSTAGE_FILE) \
 215                         $(PSP_VERSTAGE_SIG_FILE) \
 216                         $$(PSP_APCB_FILES) \
 217                         $(DEP_FILES) \
 218                         $(AMDFWTOOL) \
 219                         $(obj)/fmap_config.h \
 220                         $(objcbfs)/bootblock.elf # this target also creates the .map file
 221         $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
 222         rm -f $@
 223         @printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
 224         $(AMDFWTOOL) \
 225                 $(AMDFW_COMMON_ARGS) \
 226                 $(OPT_APOB_NV_SIZE) \
 227                 $(OPT_APOB_NV_BASE) \
 228                 $(OPT_VERSTAGE_FILE) \
 229                 $(OPT_VERSTAGE_SIG_FILE) \
 230                 --location $(CONFIG_AMD_FWM_POSITION) \
 231                 --multilevel \
 232                 --output $@
 233
 234 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
 235         rm -f $@
 236         @printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
 237         $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
 238                 --maxsize $(PSP_BIOSBIN_SIZE)
 239
 240 $(obj)/amdfw_a.rom: $(obj)/amdfw.rom
 241         rm -f $@
 242         @printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
 243         $(AMDFWTOOL) \
 244                 $(AMDFW_COMMON_ARGS) \
 245                 $(OPT_APOB_NV_SIZE) \
 246                 $(OPT_APOB_NV_BASE) \
 247                 --location $(call _tohex,$(CEZANNE_FW_A_POSITION)) \
 248                 --anywhere \
 249                 --multilevel \
 250                 --output $@
 251
 252 $(obj)/amdfw_b.rom: $(obj)/amdfw.rom
 253         rm -f $@
 254         @printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
 255         $(AMDFWTOOL) \
 256                 $(AMDFW_COMMON_ARGS) \
 257                 $(OPT_APOB_NV_SIZE) \
 258                 $(OPT_APOB_NV_BASE) \
 259                 --location $(call _tohex,$(CEZANNE_FW_B_POSITION)) \
 260                 --anywhere \
 261                 --multilevel \
 262                 --output $@
 263
 264
 265 ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy)
 266 cbfs-files-y += apu/amdfw_a
 267 apu/amdfw_a-file := $(obj)/amdfw_a.rom
 268 # Ensure this ends up at the beginning of the FW_MAIN_A fmap region
 269 apu/amdfw_a-position := $(AMD_FW_AB_POSITION)
 270 apu/amdfw_a-type := raw
 271 endif
 272
 273 ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy)
 274 cbfs-files-y += apu/amdfw_b
 275 apu/amdfw_b-file := $(obj)/amdfw_b.rom
 276 # Ensure this ends up at the beginning of the FW_MAIN_B fmap region
 277 apu/amdfw_b-position := $(AMD_FW_AB_POSITION)
 278 apu/amdfw_b-type := raw
 279 endif
 280
 281 endif # ($(CONFIG_SOC_AMD_CEZANNE),y)