src/soc/amd/cezanne/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpigen_pci.h>
   4 #include <amdblocks/acpi.h>
   5 #include <amdblocks/data_fabric.h>
   6 #include <amdblocks/fsp.h>
   7 #include <amdblocks/root_complex.h>
   8 #include <console/console.h>
   9 #include <device/device.h>
  10 #include <device/pci.h>
  11 #include <soc/cpu.h>
  12 #include <soc/pci_devs.h>
  13 #include <soc/southbridge.h>
  14 #include <types.h>
  15 #include "chip.h"
  16
  17 static const char *soc_acpi_name(const struct device *dev)
  18 {
  19         if (dev->path.type == DEVICE_PATH_DOMAIN)
  20                 return "PCI0";
  21
  22         if (dev->path.type != DEVICE_PATH_PCI)
  23                 return NULL;
  24
  25         printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
  26                PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
  27         return NULL;
  28 };
  29
  30 struct device_operations cezanne_pci_domain_ops = {
  31         .read_resources = amd_pci_domain_read_resources,
  32         .set_resources  = pci_domain_set_resources,
  33         .scan_bus       = amd_pci_domain_scan_bus,
  34         .init           = amd_pci_domain_init,
  35         .acpi_name      = soc_acpi_name,
  36         .acpi_fill_ssdt = pci_domain_fill_ssdt,
  37 };
  38
  39 static void soc_init(void *chip_info)
  40 {
  41         default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
  42
  43         amd_fsp_silicon_init();
  44
  45         data_fabric_print_mmio_conf();
  46
  47         fch_init(chip_info);
  48 }
  49
  50 static void soc_final(void *chip_info)
  51 {
  52         fch_final(chip_info);
  53 }
  54
  55 struct chip_operations soc_amd_cezanne_ops = {
  56         .name = "AMD Cezanne SoC",
  57         .init = soc_init,
  58         .final = soc_final
  59 };