src/soc/amd/cezanne/fsp_m_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/apob_cache.h>
   4 #include <amdblocks/ioapic.h>
   5 #include <amdblocks/memmap.h>
   6 #include <assert.h>
   7 #include <console/console.h>
   8 #include <console/uart.h>
   9 #include <device/device.h>
  10 #include <fsp/api.h>
  11 #include <soc/platform_descriptors.h>
  12 #include <soc/pci_devs.h>
  13 #include <static.h>
  14 #include <string.h>
  15 #include <types.h>
  16 #include <vendorcode/amd/fsp/cezanne/FspUsb.h>
  17 #include "chip.h"
  18
  19 __weak void mb_pre_fspm(void)
  20 {
  21 }
  22
  23 static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg,
  24                         const fsp_dxio_descriptor *descs, size_t num)
  25 {
  26         size_t i;
  27
  28         ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT,
  29                         "Too many DXIO descriptors provided.");
  30
  31         for (i = 0; i < num; i++) {
  32                 memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0]));
  33         }
  34 }
  35
  36 static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg,
  37                         const fsp_ddi_descriptor *descs, size_t num)
  38 {
  39         size_t i;
  40
  41         ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT,
  42                         "Too many DDI descriptors provided.");
  43
  44         for (i = 0; i < num; i++) {
  45                 memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0]));
  46         }
  47 }
  48
  49 static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg)
  50 {
  51         const fsp_dxio_descriptor *fsp_dxio = NULL;
  52         const fsp_ddi_descriptor *fsp_ddi = NULL;
  53         size_t num_dxio = 0;
  54         size_t num_ddi = 0;
  55
  56         mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio,
  57                                                 &fsp_ddi, &num_ddi);
  58         fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio);
  59         fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi);
  60 }
  61
  62 static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg)
  63 {
  64         mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR;
  65         mcfg->gnb_ioapic_id = GNB_IOAPIC_ID;
  66         mcfg->fch_ioapic_id = FCH_IOAPIC_ID;
  67 }
  68
  69 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
  70 {
  71         FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
  72         const struct soc_amd_cezanne_config *config = config_of_soc();
  73
  74         mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
  75
  76         mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
  77         mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
  78         mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
  79         mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
  80         mcfg->serial_port_baudrate = get_uart_baudrate();
  81         mcfg->serial_port_refclk = uart_platform_refclk();
  82
  83         /* 0 is default */
  84         mcfg->ccx_down_core_mode = config->downcore_mode;
  85         mcfg->ccx_disable_smt = config->disable_smt;
  86
  87         /* when stt_control isn't 1, FSP will ignore the other stt values */
  88         mcfg->stt_control = config->stt_control;
  89         mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count;
  90         mcfg->stt_min_limit = config->stt_min_limit;
  91         mcfg->stt_m1 = config->stt_m1;
  92         mcfg->stt_m2 = config->stt_m2;
  93         mcfg->stt_m3 = config->stt_m3;
  94         mcfg->stt_m4 = config->stt_m4;
  95         mcfg->stt_m5 = config->stt_m5;
  96         mcfg->stt_m6 = config->stt_m6;
  97         mcfg->stt_c_apu = config->stt_c_apu;
  98         mcfg->stt_c_gpu = config->stt_c_gpu;
  99         mcfg->stt_c_hs2 = config->stt_c_hs2;
 100         mcfg->stt_alpha_apu = config->stt_alpha_apu;
 101         mcfg->stt_alpha_gpu = config->stt_alpha_gpu;
 102         mcfg->stt_alpha_hs2 = config->stt_alpha_hs2;
 103         mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu;
 104         mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu;
 105         mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2;
 106         mcfg->stt_error_coeff = config->stt_error_coeff;
 107         mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient;
 108
 109         /* all following fields being 0 is a valid config */
 110         mcfg->stapm_boost = config->stapm_boost;
 111         mcfg->stapm_time_constant = config->stapm_time_constant_s;
 112         mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit;
 113         mcfg->sustained_power_limit = config->sustained_power_limit_mW;
 114         mcfg->fast_ppt_limit = config->fast_ppt_limit_mW;
 115         mcfg->slow_ppt_limit = config->slow_ppt_limit_mW;
 116         mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s;
 117         mcfg->thermctl_limit = config->thermctl_limit_degreeC;
 118
 119         /* 0 is default */
 120         mcfg->smartshift_enable = config->smartshift_enable;
 121
 122         /* 0 is default */
 123         mcfg->system_configuration = config->system_configuration;
 124
 125         /* when cppc_ctrl is 0 the other values won't be used */
 126         mcfg->cppc_ctrl = config->cppc_ctrl;
 127         mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range;
 128         mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range;
 129         mcfg->cppc_epp_max_range = config->cppc_epp_max_range;
 130         mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
 131         mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
 132
 133         /* S0i3 enable */
 134         mcfg->s0i3_enable = config->s0ix_enable;
 135         mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN);
 136
 137         /* voltage regulator telemetry settings */
 138         mcfg->telemetry_vddcrvddfull_scale_current =
 139                 config->telemetry_vddcrvddfull_scale_current_mA;
 140         mcfg->telemetry_vddcrvddoffset =
 141                 config->telemetry_vddcrvddoffset;
 142         mcfg->telemetry_vddcrsocfull_scale_current =
 143                 config->telemetry_vddcrsocfull_scale_current_mA;
 144         mcfg->telemetry_vddcrsocOffset =
 145                 config->telemetry_vddcrsocoffset;
 146
 147         /* PCIe power vs. speed */
 148         mcfg->pspp_policy = config->pspp_policy;
 149
 150         mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda));
 151         mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda));
 152         mcfg->sata_enable = is_dev_enabled(DEV_PTR(sata_0)) || is_dev_enabled(DEV_PTR(sata_1));
 153
 154         if (config->usb_phy_custom) {
 155                 /* devicetree config is const, use local copy */
 156                 static struct usb_phy_config lcl_usb_phy;
 157                 lcl_usb_phy = config->usb_phy;
 158                 lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION;
 159                 lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION;
 160                 lcl_usb_phy.TableLength = sizeof(struct usb_phy_config);
 161                 if ((uintptr_t)&lcl_usb_phy <= UINT32_MAX) {
 162                         mcfg->usb_phy_ptr = (uint32_t)(uintptr_t)&lcl_usb_phy;
 163                 } else {
 164                         printk(BIOS_ERR, "USB PHY config struct above 4GB; can't pass USB PHY "
 165                                          "configuration to 32 bit FSP.\n");
 166                         mcfg->usb_phy_ptr = 0;
 167                 }
 168         } else {
 169                 mcfg->usb_phy_ptr = 0;
 170         }
 171
 172         if (config->edp_phy_override) {
 173                 mcfg->edp_phy_override = config->edp_phy_override;
 174                 mcfg->edp_physel = config->edp_physel;
 175                 mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level;
 176                 mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main;
 177                 mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre;
 178                 mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post;
 179                 mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl;
 180         }
 181
 182         fsp_fill_pcie_ddi_descriptors(mcfg);
 183         fsp_assign_ioapic_upds(mcfg);
 184         mb_pre_fspm();
 185 }