src/soc/amd/phoenix/fch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/acpi.h>
   4 #include <amdblocks/acpimmio.h>
   5 #include <amdblocks/amd_pci_util.h>
   6 #include <amdblocks/gpio.h>
   7 #include <amdblocks/pci_clk_req.h>
   8 #include <amdblocks/reset.h>
   9 #include <amdblocks/smi.h>
  10 #include <bootstate.h>
  11 #include <cpu/x86/smm.h>
  12 #include <amdblocks/i2c.h>
  13 #include <soc/amd_pci_int_defs.h>
  14 #include <soc/iomap.h>
  15 #include <soc/i2c.h>
  16 #include <soc/smi.h>
  17 #include <soc/southbridge.h>
  18 #include <static.h>
  19 #include "chip.h"
  20
  21 /*
  22  * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
  23  * provides a visible association with the index, therefore helping
  24  * maintainability of table. If a new index/name is defined in
  25  * amd_pci_int_defs.h, just add the pair at the end of this table.
  26  * Order is not important.
  27  */
  28 static const struct irq_idx_name irq_association[] = {
  29         { PIRQ_A,       "INTA#" },
  30         { PIRQ_B,       "INTB#" },
  31         { PIRQ_C,       "INTC#" },
  32         { PIRQ_D,       "INTD#" },
  33         { PIRQ_E,       "INTE#" },
  34         { PIRQ_F,       "INTF#/GENINT2" },
  35         { PIRQ_G,       "INTG#" },
  36         { PIRQ_H,       "INTH#" },
  37         { PIRQ_MISC,    "Misc" },
  38         { PIRQ_MISC0,   "Misc0" },
  39         { PIRQ_HPET_L,  "HPET_L" },
  40         { PIRQ_HPET_H,  "HPET_H" },
  41         { PIRQ_SIRQA,   "Ser IRQ INTA" },
  42         { PIRQ_SIRQB,   "Ser IRQ INTB" },
  43         { PIRQ_SIRQC,   "Ser IRQ INTC" },
  44         { PIRQ_SIRQD,   "Ser IRQ INTD" },
  45         { PIRQ_SCI,     "SCI" },
  46         { PIRQ_SMBUS,   "SMBUS" },
  47         { PIRQ_ASF,     "ASF" },
  48         { PIRQ_PMON,    "PerMon" },
  49         { PIRQ_SDIO,    "SDIO" },
  50         { PIRQ_CIR,     "CIR" },
  51         { PIRQ_GPIOA,   "GPIOa" },
  52         { PIRQ_GPIOB,   "GPIOb" },
  53         { PIRQ_GPIOC,   "GPIOc" },
  54         { PIRQ_GSCI,    "GEventSci" },
  55         { PIRQ_GSMI,    "GEventSmi" },
  56         { PIRQ_GPIO,    "GPIO" },
  57         { PIRQ_I2C0,    "I2C0" },
  58         { PIRQ_I2C1,    "I2C1" },
  59         { PIRQ_I2C2,    "I2C2" },
  60         { PIRQ_I2C3,    "I2C3" },
  61         { PIRQ_UART0,   "UART0" },
  62         { PIRQ_UART1,   "UART1" },
  63         { PIRQ_UART4,   "UART4" },
  64         { PIRQ_UART2,   "UART2" },
  65         { PIRQ_UART3,   "UART3" },
  66 };
  67
  68 const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
  69 {
  70         *size = ARRAY_SIZE(irq_association);
  71         return irq_association;
  72 }
  73
  74 static void fch_clk_output_48Mhz(void)
  75 {
  76         uint32_t ctrl = misc_read32(MISC_CLK_CNTL0);
  77         /* Enable BP_X48M0 Clock Output */
  78         ctrl |= BP_X48M0_OUTPUT_EN;
  79         /* Disable clock output in S0i3 */
  80         ctrl |= BP_X48M0_S0I3_DIS;
  81         misc_write32(MISC_CLK_CNTL0, ctrl);
  82 }
  83
  84 static void fch_init_acpi_ports(void)
  85 {
  86         u32 reg;
  87
  88         /* We use some of these ports in SMM regardless of whether or not
  89          * ACPI tables are generated. Enable these ports indiscriminately.
  90          */
  91
  92         if (CONFIG(PLATFORM_USES_FSP2_0)) {
  93                 pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
  94                 pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
  95                 pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
  96                 pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
  97         }
  98
  99         if (CONFIG(HAVE_SMI_HANDLER)) {
 100                 /* APMC - SMI Command Port */
 101                 pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
 102                 configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
 103
 104                 /* SMI on SlpTyp requires sending SMI before completion
 105                    response of the I/O write. */
 106                 reg = pm_read32(PM_PCI_CTRL);
 107                 reg |= FORCE_SLPSTATE_RETRY;
 108                 pm_write32(PM_PCI_CTRL, reg);
 109
 110                 /* Disable SlpTyp feature */
 111                 reg = pm_read8(PM_RST_CTRL1);
 112                 reg &= ~SLPTYPE_CONTROL_EN;
 113                 pm_write8(PM_RST_CTRL1, reg);
 114
 115                 configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
 116         } else {
 117                 pm_write16(PM_ACPI_SMI_CMD, 0);
 118         }
 119
 120         /* Decode ACPI registers and enable standard features */
 121         pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
 122                                 PM_ACPI_GLOBAL_EN |
 123                                 PM_ACPI_RTC_EN_EN |
 124                                 PM_ACPI_TIMER_EN_EN);
 125 }
 126
 127 /* configure the general purpose PCIe clock outputs according to the devicetree settings */
 128 static void gpp_clk_setup(void)
 129 {
 130         struct soc_amd_phoenix_config *cfg = config_of_soc();
 131         gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
 132 }
 133
 134 static void cgpll_clock_gate_init(void)
 135 {
 136         uint32_t t;
 137
 138         t = misc_read32(MISC_CLKGATEDCNTL);
 139         t |= ALINKCLK_GATEOFFEN;
 140         t |= BLINKCLK_GATEOFFEN;
 141         t |= XTAL_PAD_S0I3_TURNOFF_EN;
 142         t |= XTAL_PAD_S3_TURNOFF_EN;
 143         t |= XTAL_PAD_S5_TURNOFF_EN;
 144         misc_write32(MISC_CLKGATEDCNTL, t);
 145
 146         t = misc_read32(MISC_CGPLL_CONFIGURATION0);
 147         t |= USB_PHY_CMCLK_S3_DIS;
 148         t |= USB_PHY_CMCLK_S0I3_DIS;
 149         t |= USB_PHY_CMCLK_S5_DIS;
 150         misc_write32(MISC_CGPLL_CONFIGURATION0, t);
 151
 152         t = pm_read32(PM_ISACONTROL);
 153         t |= ABCLKGATEEN;
 154         pm_write32(PM_ISACONTROL, t);
 155 }
 156
 157 void fch_init(void *chip_info)
 158 {
 159         set_resets_to_cold();
 160         i2c_soc_init();
 161         fch_init_acpi_ports();
 162
 163         acpi_pm_gpe_add_events_print_events();
 164         gpio_add_events();
 165
 166         if (CONFIG(PLATFORM_USES_FSP2_0))
 167                 gpp_clk_setup();
 168
 169         fch_clk_output_48Mhz();
 170         cgpll_clock_gate_init();
 171 }
 172
 173 void fch_final(void *chip_info)
 174 {
 175 }
 176
 177 static void set_pci_irqs(void *unused)
 178 {
 179         /* Write PCI_INTR regs 0xC00/0xC01 */
 180         write_pci_int_table();
 181
 182         /* pirq_data is consumed by `write_pci_cfg_irqs` */
 183         populate_pirq_data();
 184
 185         /* Write IRQs for all devicetree enabled devices */
 186         write_pci_cfg_irqs();
 187 }
 188
 189 /*
 190  * Hook this function into the PCI state machine
 191  * on entry into BS_DEV_ENABLE.
 192  */
 193 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);