src/soc/amd/stoneyridge/cpu.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/cpu.h>
   4 #include <amdblocks/iomap.h>
   5 #include <amdblocks/mca.h>
   6 #include <amdblocks/reset.h>
   7 #include <cpu/amd/msr.h>
   8 #include <cpu/cpu.h>
   9 #include <cpu/x86/mp.h>
  10 #include <cpu/x86/mtrr.h>
  11 #include <cpu/x86/msr.h>
  12 #include <device/device.h>
  13 #include <device/pci_ops.h>
  14 #include <soc/pci_devs.h>
  15 #include <soc/cpu.h>
  16 #include <soc/iomap.h>
  17 #include <console/console.h>
  18 #include <types.h>
  19
  20 /*
  21  * MP and SMM loading initialization.
  22  */
  23 void mp_init_cpus(struct bus *cpu_bus)
  24 {
  25         extern const struct mp_ops amd_mp_ops_with_smm;
  26         if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
  27                 die_with_post_code(POSTCODE_HW_INIT_FAILURE,
  28                                 "mp_init_with_smm failed. Halting.\n");
  29
  30         /* The flash is now no longer cacheable. Reset to WP for performance. */
  31         mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
  32                             FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
  33
  34         set_warm_reset_flag();
  35 }
  36
  37 static void model_15_init(struct device *dev)
  38 {
  39         check_mca();
  40
  41         /*
  42          * Per AMD, sync an undocumented MSR with the PSP base address.
  43          * Experiments showed that if you write to the MSR after it has
  44          * been previously programmed, it causes a general protection fault.
  45          * Also, the MSR survives warm reset and S3 cycles, so we need to
  46          * test if it was previously written before writing to it.
  47          */
  48         msr_t psp_msr;
  49         uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
  50         psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
  51         psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
  52         psp_msr = rdmsr(PSP_ADDR_MSR);
  53         if (psp_msr.lo == 0) {
  54                 psp_msr.lo = psp_bar;
  55                 wrmsr(PSP_ADDR_MSR, psp_msr);
  56         }
  57 }
  58
  59 static struct device_operations cpu_dev_ops = {
  60         .init = model_15_init,
  61 };
  62
  63 static struct cpu_device_id cpu_table[] = {
  64         { X86_VENDOR_AMD, CPUID_FROM_FMS(0x15, 0x60, 0), CPUID_ALL_STEPPINGS_MASK },
  65         { X86_VENDOR_AMD, CPUID_FROM_FMS(0x15, 0x70, 0), CPUID_ALL_STEPPINGS_MASK },
  66         CPU_TABLE_END
  67 };
  68
  69 static const struct cpu_driver model_15 __cpu_driver = {
  70         .ops      = &cpu_dev_ops,
  71         .id_table = cpu_table,
  72 };