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HEAD
mb/google/brya/var/orisa: Update Type C DisplayPort HPD Configuration
[coreboot2.git]
/
src
/
soc
/
example
/
min86
/
cache_as_ram.S
blob
5c5066d7ea12d99be12301b28310697df6cd8f49
1
/* SPDX-License-Identifier: GPL-2.0-only */
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.section .init, "ax", @progbits
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.global bootblock_pre_c_entry
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.code32
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bootblock_pre_c_entry:
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call bootblock_c_entry_bist
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.Lhlt:
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hlt
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jmp .Lhlt