src/soc/intel/braswell/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ops.h>
   7 #include <fsp/util.h>
   8 #include <soc/pci_devs.h>
   9 #include <soc/ramstage.h>
  10
  11 #include "chip.h"
  12
  13 static struct device_operations pci_domain_ops = {
  14         .read_resources   = pci_domain_read_resources,
  15         .set_resources    = pci_domain_set_resources,
  16         .scan_bus         = pci_host_bridge_scan_bus,
  17 };
  18
  19 static struct device_operations cpu_bus_ops = {
  20         .read_resources   = noop_read_resources,
  21         .set_resources    = noop_set_resources,
  22         .init             = mp_cpu_bus_init,
  23 };
  24
  25 static void enable_dev(struct device *dev)
  26 {
  27         /* Set the operations if it is a special bus type */
  28         if (dev->path.type == DEVICE_PATH_DOMAIN) {
  29                 dev->ops = &pci_domain_ops;
  30
  31         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
  32                 dev->ops = &cpu_bus_ops;
  33
  34         } else if (dev->path.type == DEVICE_PATH_PCI) {
  35                 /* Handle south cluster enablement. */
  36                 if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
  37                     (dev->ops == NULL || dev->ops->enable == NULL)) {
  38                         southcluster_enable_dev(dev);
  39                 }
  40         }
  41 }
  42
  43 __weak void board_silicon_USB2_override(SILICON_INIT_UPD *params)
  44 {
  45 }
  46
  47 void soc_silicon_init_params(SILICON_INIT_UPD *params)
  48 {
  49         struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
  50         struct soc_intel_braswell_config *config;
  51
  52         if (!dev) {
  53                 printk(BIOS_ERR, "Error! Device (%s) not found, %s!\n",
  54                         dev_path(dev), __func__);
  55                 return;
  56         }
  57
  58         config = config_of(dev);
  59
  60         /* Set the parameters for SiliconInit */
  61         printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n");
  62         params->PcdSdcardMode                   = config->PcdSdcardMode;
  63         params->PcdEnableHsuart0                = config->PcdEnableHsuart0;
  64         params->PcdEnableHsuart1                = config->PcdEnableHsuart1;
  65         params->PcdEnableAzalia                 = config->PcdEnableAzalia;
  66         params->PcdEnableSata                   = config->PcdEnableSata;
  67         params->PcdEnableXhci                   = config->PcdEnableXhci;
  68         params->PcdEnableLpe                    = config->PcdEnableLpe;
  69         params->PcdEnableDma0                   = config->PcdEnableDma0;
  70         params->PcdEnableDma1                   = config->PcdEnableDma1;
  71         params->PcdEnableI2C0                   = config->PcdEnableI2C0;
  72         params->PcdEnableI2C1                   = config->PcdEnableI2C1;
  73         params->PcdEnableI2C2                   = config->PcdEnableI2C2;
  74         params->PcdEnableI2C3                   = config->PcdEnableI2C3;
  75         params->PcdEnableI2C4                   = config->PcdEnableI2C4;
  76         params->PcdEnableI2C5                   = config->PcdEnableI2C5;
  77         params->PcdEnableI2C6                   = config->PcdEnableI2C6;
  78         params->GraphicsConfigPtr               = 0;
  79         params->AzaliaConfigPtr                 = 0;
  80         params->PunitPwrConfigDisable           = config->PunitPwrConfigDisable;
  81         params->ChvSvidConfig                   = config->ChvSvidConfig;
  82         params->DptfDisable                     = !is_devfn_enabled(PCI_DEVFN(PUNIT_DEV, 0));
  83         params->PcdEmmcMode                     = config->PcdEmmcMode;
  84         params->PcdUsb3ClkSsc                   = 1;
  85         params->PcdDispClkSsc                   = 1;
  86         params->PcdSataClkSsc                   = 1;
  87
  88         params->Usb2Port0PerPortPeTxiSet        = config->Usb2Port0PerPortPeTxiSet;
  89         params->Usb2Port0PerPortTxiSet          = config->Usb2Port0PerPortTxiSet;
  90         params->Usb2Port0IUsbTxEmphasisEn       = config->Usb2Port0IUsbTxEmphasisEn;
  91         params->Usb2Port0PerPortTxPeHalf        = config->Usb2Port0PerPortTxPeHalf;
  92
  93         params->Usb2Port1PerPortPeTxiSet        = config->Usb2Port1PerPortPeTxiSet;
  94         params->Usb2Port1PerPortTxiSet          = config->Usb2Port1PerPortTxiSet;
  95         params->Usb2Port1IUsbTxEmphasisEn       = config->Usb2Port1IUsbTxEmphasisEn;
  96         params->Usb2Port1PerPortTxPeHalf        = config->Usb2Port1PerPortTxPeHalf;
  97
  98         params->Usb2Port2PerPortPeTxiSet        = config->Usb2Port2PerPortPeTxiSet;
  99         params->Usb2Port2PerPortTxiSet          = config->Usb2Port2PerPortTxiSet;
 100         params->Usb2Port2IUsbTxEmphasisEn       = config->Usb2Port2IUsbTxEmphasisEn;
 101         params->Usb2Port2PerPortTxPeHalf        = config->Usb2Port2PerPortTxPeHalf;
 102
 103         params->Usb2Port3PerPortPeTxiSet        = config->Usb2Port3PerPortPeTxiSet;
 104         params->Usb2Port3PerPortTxiSet          = config->Usb2Port3PerPortTxiSet;
 105         params->Usb2Port3IUsbTxEmphasisEn       = config->Usb2Port3IUsbTxEmphasisEn;
 106         params->Usb2Port3PerPortTxPeHalf        = config->Usb2Port3PerPortTxPeHalf;
 107
 108         params->Usb2Port4PerPortPeTxiSet        = config->Usb2Port4PerPortPeTxiSet;
 109         params->Usb2Port4PerPortTxiSet          = config->Usb2Port4PerPortTxiSet;
 110         params->Usb2Port4IUsbTxEmphasisEn       = config->Usb2Port4IUsbTxEmphasisEn;
 111         params->Usb2Port4PerPortTxPeHalf        = config->Usb2Port4PerPortTxPeHalf;
 112
 113         params->Usb3Lane0Ow2tapgen2deemph3p5    = config->Usb3Lane0Ow2tapgen2deemph3p5;
 114         params->Usb3Lane1Ow2tapgen2deemph3p5    = config->Usb3Lane1Ow2tapgen2deemph3p5;
 115         params->Usb3Lane2Ow2tapgen2deemph3p5    = config->Usb3Lane2Ow2tapgen2deemph3p5;
 116         params->Usb3Lane3Ow2tapgen2deemph3p5    = config->Usb3Lane3Ow2tapgen2deemph3p5;
 117
 118         params->PcdSataInterfaceSpeed           = 3;
 119         params->PcdPchUsbSsicPort               = config->PcdPchUsbSsicPort;
 120         params->PcdPchUsbHsicPort               = config->PcdPchUsbHsicPort;
 121         params->PcdPcieRootPortSpeed            = 0;
 122         params->PcdPchSsicEnable                = config->PcdPchSsicEnable;
 123         params->PcdRtcLock                      = 0;
 124         params->PMIC_I2CBus                     = config->PMIC_I2CBus;
 125         params->ISPEnable                       = config->ISPEnable;
 126         params->ISPPciDevConfig                 = config->ISPPciDevConfig;
 127         params->PcdSdDetectChk                  = config->PcdSdDetectChk;
 128         params->I2C0Frequency                   = config->I2C0Frequency;
 129         params->I2C1Frequency                   = config->I2C1Frequency;
 130         params->I2C2Frequency                   = config->I2C2Frequency;
 131         params->I2C3Frequency                   = config->I2C3Frequency;
 132         params->I2C4Frequency                   = config->I2C4Frequency;
 133         params->I2C5Frequency                   = config->I2C5Frequency;
 134         params->I2C6Frequency                   = config->I2C6Frequency;
 135
 136         board_silicon_USB2_override(params);
 137 }
 138
 139 void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
 140 {
 141         /* Display the parameters for SiliconInit */
 142         printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
 143
 144         fsp_display_upd_value("PcdSdcardMode", 1,
 145                           old->PcdSdcardMode,
 146                           new->PcdSdcardMode);
 147         fsp_display_upd_value("PcdEnableHsuart0", 1,
 148                           old->PcdEnableHsuart0,
 149                           new->PcdEnableHsuart0);
 150         fsp_display_upd_value("PcdEnableHsuart1", 1,
 151                           old->PcdEnableHsuart1,
 152                           new->PcdEnableHsuart1);
 153         fsp_display_upd_value("PcdEnableAzalia", 1,
 154                           old->PcdEnableAzalia,
 155                           new->PcdEnableAzalia);
 156         fsp_display_upd_value("AzaliaConfigPtr", 4,
 157                 (uint32_t)old->AzaliaConfigPtr,
 158                 (uint32_t)new->AzaliaConfigPtr);
 159
 160         fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, new->PcdEnableSata);
 161         fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, new->PcdEnableXhci);
 162         fsp_display_upd_value("PcdEnableLpe",  1, old->PcdEnableLpe,  new->PcdEnableLpe);
 163         fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, new->PcdEnableDma0);
 164         fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, new->PcdEnableDma1);
 165         fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, new->PcdEnableI2C0);
 166         fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, new->PcdEnableI2C1);
 167         fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, new->PcdEnableI2C2);
 168         fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, new->PcdEnableI2C3);
 169         fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, new->PcdEnableI2C4);
 170         fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, new->PcdEnableI2C5);
 171         fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, new->PcdEnableI2C6);
 172
 173         fsp_display_upd_value("PcdGraphicsConfigPtr", 4,
 174                           old->GraphicsConfigPtr,
 175                           new->GraphicsConfigPtr);
 176         fsp_display_upd_value("GpioFamilyInitTablePtr", 4,
 177                 (uint32_t)old->GpioFamilyInitTablePtr,
 178                 (uint32_t)new->GpioFamilyInitTablePtr);
 179         fsp_display_upd_value("GpioPadInitTablePtr", 4,
 180                 (uint32_t)old->GpioPadInitTablePtr,
 181                 (uint32_t)new->GpioPadInitTablePtr);
 182         fsp_display_upd_value("PunitPwrConfigDisable", 1,
 183                           old->PunitPwrConfigDisable,
 184                           new->PunitPwrConfigDisable);
 185
 186         fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, new->ChvSvidConfig);
 187         fsp_display_upd_value("DptfDisable",   1, old->DptfDisable,   new->DptfDisable);
 188         fsp_display_upd_value("PcdEmmcMode",   1, old->PcdEmmcMode,   new->PcdEmmcMode);
 189         fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, new->PcdUsb3ClkSsc);
 190         fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, new->PcdDispClkSsc);
 191         fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, new->PcdSataClkSsc);
 192
 193         fsp_display_upd_value("Usb2Port0PerPortPeTxiSet", 1,
 194                           old->Usb2Port0PerPortPeTxiSet,
 195                           new->Usb2Port0PerPortPeTxiSet);
 196         fsp_display_upd_value("Usb2Port0PerPortTxiSet", 1,
 197                           old->Usb2Port0PerPortTxiSet,
 198                           new->Usb2Port0PerPortTxiSet);
 199         fsp_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1,
 200                           old->Usb2Port0IUsbTxEmphasisEn,
 201                           new->Usb2Port0IUsbTxEmphasisEn);
 202         fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1,
 203                           old->Usb2Port0PerPortTxPeHalf,
 204                           new->Usb2Port0PerPortTxPeHalf);
 205         fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1,
 206                           old->Usb2Port1PerPortPeTxiSet,
 207                           new->Usb2Port1PerPortPeTxiSet);
 208         fsp_display_upd_value("Usb2Port1PerPortTxiSet", 1,
 209                           old->Usb2Port1PerPortTxiSet,
 210                           new->Usb2Port1PerPortTxiSet);
 211         fsp_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1,
 212                           old->Usb2Port1IUsbTxEmphasisEn,
 213                           new->Usb2Port1IUsbTxEmphasisEn);
 214         fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1,
 215                           old->Usb2Port1PerPortTxPeHalf,
 216                           new->Usb2Port1PerPortTxPeHalf);
 217         fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1,
 218                           old->Usb2Port2PerPortPeTxiSet,
 219                           new->Usb2Port2PerPortPeTxiSet);
 220         fsp_display_upd_value("Usb2Port2PerPortTxiSet", 1,
 221                           old->Usb2Port2PerPortTxiSet,
 222                           new->Usb2Port2PerPortTxiSet);
 223         fsp_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1,
 224                           old->Usb2Port2IUsbTxEmphasisEn,
 225                           new->Usb2Port2IUsbTxEmphasisEn);
 226         fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1,
 227                           old->Usb2Port2PerPortTxPeHalf,
 228                           new->Usb2Port2PerPortTxPeHalf);
 229         fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1,
 230                           old->Usb2Port3PerPortPeTxiSet,
 231                           new->Usb2Port3PerPortPeTxiSet);
 232         fsp_display_upd_value("Usb2Port3PerPortTxiSet", 1,
 233                           old->Usb2Port3PerPortTxiSet,
 234                           new->Usb2Port3PerPortTxiSet);
 235         fsp_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1,
 236                           old->Usb2Port3IUsbTxEmphasisEn,
 237                           new->Usb2Port3IUsbTxEmphasisEn);
 238         fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1,
 239                           old->Usb2Port3PerPortTxPeHalf,
 240                           new->Usb2Port3PerPortTxPeHalf);
 241         fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1,
 242                           old->Usb2Port4PerPortPeTxiSet,
 243                           new->Usb2Port4PerPortPeTxiSet);
 244         fsp_display_upd_value("Usb2Port4PerPortTxiSet", 1,
 245                           old->Usb2Port4PerPortTxiSet,
 246                           new->Usb2Port4PerPortTxiSet);
 247         fsp_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1,
 248                           old->Usb2Port4IUsbTxEmphasisEn,
 249                           new->Usb2Port4IUsbTxEmphasisEn);
 250         fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1,
 251                           old->Usb2Port4PerPortTxPeHalf,
 252                           new->Usb2Port4PerPortTxPeHalf);
 253         fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1,
 254                           old->Usb3Lane0Ow2tapgen2deemph3p5,
 255                           new->Usb3Lane0Ow2tapgen2deemph3p5);
 256         fsp_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1,
 257                           old->Usb3Lane1Ow2tapgen2deemph3p5,
 258                           new->Usb3Lane1Ow2tapgen2deemph3p5);
 259         fsp_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1,
 260                           old->Usb3Lane2Ow2tapgen2deemph3p5,
 261                           new->Usb3Lane2Ow2tapgen2deemph3p5);
 262         fsp_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1,
 263                           old->Usb3Lane3Ow2tapgen2deemph3p5,
 264                           new->Usb3Lane3Ow2tapgen2deemph3p5);
 265         fsp_display_upd_value("PcdSataInterfaceSpeed", 1,
 266                           old->PcdSataInterfaceSpeed,
 267                           new->PcdSataInterfaceSpeed);
 268         fsp_display_upd_value("PcdPchUsbSsicPort", 1,
 269                           old->PcdPchUsbSsicPort,
 270                           new->PcdPchUsbSsicPort);
 271         fsp_display_upd_value("PcdPchUsbHsicPort", 1,
 272                           old->PcdPchUsbHsicPort,
 273                           new->PcdPchUsbHsicPort);
 274         fsp_display_upd_value("PcdPcieRootPortSpeed", 1,
 275                           old->PcdPcieRootPortSpeed,
 276                           new->PcdPcieRootPortSpeed);
 277         fsp_display_upd_value("PcdPchSsicEnable", 1,
 278                           old->PcdPchSsicEnable,
 279                           new->PcdPchSsicEnable);
 280
 281         fsp_display_upd_value("PcdLogoPtr",      4, old->PcdLogoPtr,      new->PcdLogoPtr);
 282         fsp_display_upd_value("PcdLogoSize",     4, old->PcdLogoSize,     new->PcdLogoSize);
 283         fsp_display_upd_value("PcdRtcLock",      1, old->PcdRtcLock,      new->PcdRtcLock);
 284         fsp_display_upd_value("PMIC_I2CBus",     1, old->PMIC_I2CBus,     new->PMIC_I2CBus);
 285         fsp_display_upd_value("ISPEnable",       1, old->ISPEnable,       new->ISPEnable);
 286         fsp_display_upd_value("ISPPciDevConfig", 1, old->ISPPciDevConfig, new->ISPPciDevConfig);
 287         fsp_display_upd_value("PcdSdDetectChk",  1, old->PcdSdDetectChk,  new->PcdSdDetectChk);
 288 }
 289
 290 /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
 291 static void soc_init(void *chip_info)
 292 {
 293         soc_init_pre_device(chip_info);
 294 }
 295
 296 struct chip_operations soc_intel_braswell_ops = {
 297         .name = "Intel Braswell SoC",
 298         .enable_dev = enable_dev,
 299         .init       = soc_init,
 300 };
 301
 302 struct pci_operations soc_pci_ops = {
 303         .set_subsystem = &pci_dev_set_subsystem,
 304 };
 305
 306 /**
 307   Return SoC stepping type
 308
 309   @retval SOC_STEPPING            SoC stepping type
 310 **/
 311 int SocStepping(void)
 312 {
 313         struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
 314         const u8 revid = pci_read_config8(dev, 0x8);
 315
 316         switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {
 317         case V_PCH_LPC_RID_A0:
 318                 return SocA0;
 319         case V_PCH_LPC_RID_A1:
 320                 return SocA1;
 321         case V_PCH_LPC_RID_A2:
 322                 return SocA2;
 323         case V_PCH_LPC_RID_A3:
 324                 return SocA3;
 325         case V_PCH_LPC_RID_A4:
 326                 return SocA4;
 327         case V_PCH_LPC_RID_A5:
 328                 return SocA5;
 329         case V_PCH_LPC_RID_A6:
 330                 return SocA6;
 331         case V_PCH_LPC_RID_A7:
 332                 return SocA7;
 333         case V_PCH_LPC_RID_B0:
 334                 return SocB0;
 335         case V_PCH_LPC_RID_B1:
 336                 return SocB1;
 337         case V_PCH_LPC_RID_B2:
 338                 return SocB2;
 339         case V_PCH_LPC_RID_B3:
 340                 return SocB3;
 341         case V_PCH_LPC_RID_B4:
 342                 return SocB4;
 343         case V_PCH_LPC_RID_B5:
 344                 return SocB5;
 345         case V_PCH_LPC_RID_B6:
 346                 return SocB6;
 347         case V_PCH_LPC_RID_B7:
 348                 return SocB7;
 349         case V_PCH_LPC_RID_C0:
 350                 return SocC0;
 351         case V_PCH_LPC_RID_C1:
 352                 return SocC1;
 353         case V_PCH_LPC_RID_C2:
 354                 return SocC2;
 355         case V_PCH_LPC_RID_C3:
 356                 return SocC3;
 357         case V_PCH_LPC_RID_C4:
 358                 return SocC4;
 359         case V_PCH_LPC_RID_C5:
 360                 return SocC5;
 361         case V_PCH_LPC_RID_C6:
 362                 return SocC6;
 363         case V_PCH_LPC_RID_C7:
 364                 return SocC7;
 365         case V_PCH_LPC_RID_D0:
 366                 return SocD0;
 367         case V_PCH_LPC_RID_D1:
 368                 return SocD1;
 369         case V_PCH_LPC_RID_D2:
 370                 return SocD2;
 371         case V_PCH_LPC_RID_D3:
 372                 return SocD3;
 373         case V_PCH_LPC_RID_D4:
 374                 return SocD4;
 375         case V_PCH_LPC_RID_D5:
 376                 return SocD5;
 377         case V_PCH_LPC_RID_D6:
 378                 return SocD6;
 379         case V_PCH_LPC_RID_D7:
 380                 return SocD7;
 381         default:
 382                 return SocSteppingMax;
 383         }
 384 }