mb/google/brya/var/orisa: Update Type C DisplayPort HPD Configuration
[coreboot2.git] / src / soc / intel / braswell / memmap.c
blob3c3ad74b713afd25035334ca23a7280f8003dad0
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <cbmem.h>
4 #include <cpu/x86/smm.h>
5 #include <soc/iosf.h>
7 static size_t smm_region_size(void)
9 u32 smm_size;
10 smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF;
11 smm_size -= iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF;
12 smm_size = (smm_size + 1) << 20;
13 return smm_size;
16 void smm_region(uintptr_t *start, size_t *size)
18 *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
19 *size = smm_region_size();
22 uintptr_t cbmem_top_chipset(void)
24 uintptr_t smm_base;
25 size_t smm_size;
28 * +-------------------------+ Top of RAM (aligned)
29 * | System Management Mode |
30 * | code and data | Length: CONFIG_SMM_TSEG_SIZE
31 * | (TSEG) |
32 * +-------------------------+ SMM base (aligned)
33 * | |
34 * | Chipset Reserved Memory | Length: Multiple of CONFIG_SMM_TSEG_SIZE
35 * | |
36 * +-------------------------+ top_of_ram (aligned)
37 * | |
38 * | CBMEM Root |
39 * | |
40 * +-------------------------+
41 * | |
42 * | FSP Reserved Memory |
43 * | |
44 * +-------------------------+
45 * | |
46 * | Various CBMEM Entries |
47 * | |
48 * +-------------------------+ top_of_stack (8 byte aligned)
49 * | |
50 * | stack (CBMEM Entry) |
51 * | |
52 * +-------------------------+
55 smm_region(&smm_base, &smm_size);
56 return smm_base;