src/soc/intel/braswell/tsc_freq.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cpu/x86/msr.h>
   4 #include <cpu/x86/tsc.h>
   5 #include <soc/msr.h>
   6
   7 static const unsigned int cpu_bus_clk_freq_table[] = {
   8         83333,
   9         100000,
  10         133333,
  11         116666,
  12         80000,
  13         93333,
  14         90000,
  15         88900,
  16         87500
  17 };
  18
  19 unsigned int cpu_bus_freq_khz(void)
  20 {
  21         msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
  22
  23         if ((clk_info.lo & 0xf) < ARRAY_SIZE(cpu_bus_clk_freq_table))
  24                 return cpu_bus_clk_freq_table[clk_info.lo & 0xf];
  25
  26         return 0;
  27 }
  28
  29 unsigned long tsc_freq_mhz(void)
  30 {
  31         msr_t platform_info;
  32         unsigned int bclk_khz = cpu_bus_freq_khz();
  33
  34         if (!bclk_khz)
  35                 return 0;
  36
  37         platform_info = rdmsr(MSR_PLATFORM_INFO);
  38         return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
  39 }
  40
  41 void set_max_freq(void)
  42 {
  43         msr_t perf_ctl;
  44         msr_t msr;
  45
  46         /* Enable Intel SpeedStep */
  47         msr = rdmsr(IA32_MISC_ENABLE);
  48         msr.lo |= (1 << 16);
  49         wrmsr(IA32_MISC_ENABLE, msr);
  50
  51         /* Enable Burst Mode */
  52         msr = rdmsr(IA32_MISC_ENABLE);
  53         msr.hi = 0;
  54         wrmsr(IA32_MISC_ENABLE, msr);
  55
  56         /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of the PERF_CTL */
  57         msr = rdmsr(MSR_IACORE_TURBO_RATIOS);
  58         perf_ctl.lo = (msr.lo & 0x003f0000) >> 8;
  59
  60         /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of the PERF_CTL */
  61         msr = rdmsr(MSR_IACORE_TURBO_VIDS);
  62         perf_ctl.lo |= (msr.lo & 0x007f0000) >> 16;
  63         perf_ctl.hi = 0;
  64
  65         wrmsr(IA32_PERF_CTL, perf_ctl);
  66 }