src/soc/intel/cannonlake/cpu.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/pci.h>
   5 #include <cpu/x86/mp.h>
   6 #include <cpu/x86/msr.h>
   7 #include <cpu/intel/smm_reloc.h>
   8 #include <cpu/intel/turbo.h>
   9 #include <intelblocks/cpulib.h>
  10 #include <intelblocks/mp_init.h>
  11 #include <soc/cpu.h>
  12 #include <soc/msr.h>
  13 #include <soc/pci_devs.h>
  14 #include <soc/systemagent.h>
  15 #include <cpu/x86/mtrr.h>
  16 #include <cpu/intel/microcode.h>
  17 #include <cpu/intel/common/common.h>
  18 #include <static.h>
  19 #include <types.h>
  20
  21 #include "chip.h"
  22
  23 bool cpu_soc_is_in_untrusted_mode(void)
  24 {
  25         msr_t msr;
  26
  27         msr = rdmsr(MSR_BIOS_DONE);
  28         return !!(msr.lo & ENABLE_IA_UNTRUSTED);
  29 }
  30
  31 void cpu_soc_bios_done(void)
  32 {
  33         msr_t msr;
  34
  35         msr = rdmsr(MSR_BIOS_DONE);
  36         msr.lo |= ENABLE_IA_UNTRUSTED;
  37         wrmsr(MSR_BIOS_DONE, msr);
  38 }
  39
  40 static void soc_fsp_load(void)
  41 {
  42         fsps_load();
  43 }
  44
  45 static void configure_misc(void)
  46 {
  47         msr_t msr;
  48
  49         config_t *conf = config_of_soc();
  50
  51         msr = rdmsr(IA32_MISC_ENABLE);
  52         msr.lo |= (1 << 0);     /* Fast String enable */
  53         msr.lo |= (1 << 3);     /* TM1/TM2/EMTTM enable */
  54         wrmsr(IA32_MISC_ENABLE, msr);
  55
  56         /* Set EIST status */
  57         cpu_set_eist(conf->eist_enable);
  58
  59         /* Disable Thermal interrupts */
  60         msr.lo = 0;
  61         msr.hi = 0;
  62         wrmsr(IA32_THERM_INTERRUPT, msr);
  63
  64         /* Enable package critical interrupt only */
  65         msr.lo = 1 << 4;
  66         msr.hi = 0;
  67         wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
  68
  69         /* Enable PROCHOT */
  70         msr = rdmsr(MSR_POWER_CTL);
  71         msr.lo |= (1 << 0);     /* Enable Bi-directional PROCHOT as an input */
  72         msr.lo |= (1 << 18);    /* Enable Energy/Performance Bias control */
  73         msr.lo |= (1 << 23);    /* Lock it */
  74         wrmsr(MSR_POWER_CTL, msr);
  75 }
  76
  77 static void configure_c_states(const config_t *const cfg)
  78 {
  79         msr_t msr;
  80
  81         msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
  82         if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) {
  83                 msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf);
  84         }
  85         msr.lo |= CST_CFG_LOCK_MASK;
  86         wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
  87
  88         /* C-state Interrupt Response Latency Control 0 - package C3 latency */
  89         msr.hi = 0;
  90         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
  91         wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);
  92
  93         /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
  94         msr.hi = 0;
  95         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
  96         wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
  97
  98         /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
  99         msr.hi = 0;
 100         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
 101         wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 102
 103         /* C-state Interrupt Response Latency Control 3 - package C8 */
 104         msr.hi = 0;
 105         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
 106         wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 107
 108         /* C-state Interrupt Response Latency Control 4 - package C9 */
 109         msr.hi = 0;
 110         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
 111         wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 112
 113         /* C-state Interrupt Response Latency Control 5 - package C10 */
 114         msr.hi = 0;
 115         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
 116         wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 117 }
 118
 119 /* All CPUs including BSP will run the following function. */
 120 void soc_core_init(struct device *cpu)
 121 {
 122         config_t *cfg = config_of_soc();
 123
 124         /* Clear out pending MCEs */
 125         /* TODO(adurbin): This should only be done on a cold boot. Also, some
 126          * of these banks are core vs package scope. For now every CPU clears
 127          * every bank. */
 128         mca_configure();
 129
 130         enable_lapic_tpr();
 131
 132         /* Configure c-state interrupt response time */
 133         configure_c_states(cfg);
 134
 135         /* Configure Enhanced SpeedStep and Thermal Sensors */
 136         configure_misc();
 137
 138         set_aesni_lock();
 139
 140         enable_pm_timer_emulation();
 141
 142         /* Enable Direct Cache Access */
 143         configure_dca_cap();
 144
 145         /* Set energy policy */
 146         set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 147
 148         if (cfg->cpu_turbo_disable)
 149                 disable_turbo();
 150         else
 151                 enable_turbo();
 152
 153         /* Enable Vmx */
 154         set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !cfg->disable_vmx);
 155         set_feature_ctrl_lock();
 156 }
 157
 158 static void per_cpu_smm_trigger(void)
 159 {
 160         /* Relocate the SMM handler. */
 161         smm_relocate();
 162 }
 163
 164 void smm_lock(void)
 165 {
 166         /*
 167          * LOCK the SMM memory window and enable normal SMM.
 168          * After running this function, only a full reset can
 169          * make the SMM registers writable again. D_LCK bit
 170          * requires the PCI 0xcf8/0xcfc I/O access.
 171          */
 172         printk(BIOS_DEBUG, "Locking SMM.\n");
 173         pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 174 }
 175
 176 static void post_mp_init(void)
 177 {
 178         /* Set Max Ratio */
 179         cpu_set_max_ratio();
 180
 181         /*
 182          * Now that all APs have been relocated as well as the BSP let SMIs
 183          * start flowing.
 184          */
 185         global_smi_enable_no_pwrbtn();
 186
 187         /* Lock down the SMRAM space. */
 188         smm_lock();
 189 }
 190
 191 static const struct mp_ops mp_ops = {
 192         /*
 193          * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
 194          * that are set prior to ramstage.
 195          * Real MTRRs programming are being done after resource allocation.
 196          */
 197         .pre_mp_init = soc_fsp_load,
 198         .get_cpu_count = get_cpu_count,
 199         .get_smm_info = smm_info,
 200         .get_microcode_info = get_microcode_info,
 201         .pre_mp_smm_init = smm_initialize,
 202         .per_cpu_smm_trigger = per_cpu_smm_trigger,
 203         .relocation_handler = smm_relocation_handler,
 204         .post_mp_init = post_mp_init,
 205 };
 206
 207 void mp_init_cpus(struct bus *cpu_bus)
 208 {
 209         /* TODO: Handle mp_init_with_smm failure? */
 210         mp_init_with_smm(cpu_bus, &mp_ops);
 211
 212         /* Thermal throttle activation offset */
 213         configure_tcc_thermal_target();
 214 }
 215
 216 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 217 {
 218         msr_t msr1;
 219         msr_t msr2;
 220
 221         /*
 222          * If PRMRR/SGX is supported the FIT microcode load will set the msr
 223          * 0x08b with the Patch revision id one less than the id in the
 224          * microcode binary. The PRMRR support is indicated in the MSR
 225          * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the
 226          * same microcode during CPU initialization. If SGX is enabled, as
 227          * part of SGX BIOS initialization steps, the same microcode needs to
 228          * be reloaded after the core PRMRR MSRs are programmed.
 229          */
 230         msr1 = rdmsr(MTRR_CAP_MSR);
 231         msr2 = rdmsr(MSR_PRMRR_PHYS_BASE);
 232         if (msr2.lo && (current_patch_id == new_patch_id - 1))
 233                 return 0;
 234
 235         return (msr1.lo & MTRR_CAP_PRMRR) &&
 236                 (current_patch_id == new_patch_id - 1);
 237 }