src/soc/intel/cannonlake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <commonlib/console/post_codes.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include <device/mmio.h>
   8 #include <device/pci.h>
   9 #include <intelblocks/cpulib.h>
  10 #include <intelblocks/cse.h>
  11 #include <intelblocks/lpc_lib.h>
  12 #include <intelblocks/pcr.h>
  13 #include <intelblocks/pmclib.h>
  14 #include <intelblocks/systemagent.h>
  15 #include <intelblocks/tco.h>
  16 #include <intelblocks/thermal.h>
  17 #include <soc/p2sb.h>
  18 #include <soc/pci_devs.h>
  19 #include <soc/pcr_ids.h>
  20 #include <soc/pm.h>
  21 #include <soc/smbus.h>
  22 #include <soc/systemagent.h>
  23 #include <spi-generic.h>
  24 #include <static.h>
  25
  26 #include "chip.h"
  27
  28 #define CAMERA1_CLK             0x8000 /* Camera 1 Clock */
  29 #define CAMERA2_CLK             0x8080 /* Camera 2 Clock */
  30 #define CAM_CLK_EN              (1 << 1)
  31 #define MIPI_CLK                (1 << 0)
  32 #define HDPLL_CLK               (0 << 0)
  33
  34 static void pch_enable_isclk(void)
  35 {
  36         pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
  37         pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
  38 }
  39
  40 static void pch_handle_sideband(config_t *config)
  41 {
  42         if (config->pch_isclk)
  43                 pch_enable_isclk();
  44 }
  45
  46 static void pch_finalize(void)
  47 {
  48         uint32_t reg32;
  49         uint8_t *pmcbase;
  50         config_t *config;
  51
  52         tco_lockdown();
  53
  54         /*
  55          * Set low maximum temp threshold value used for dynamic thermal sensor
  56          * shutdown consideration.
  57          *
  58          * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
  59          * thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
  60          */
  61         pch_thermal_configuration();
  62
  63         config = config_of_soc();
  64         pmcbase = pmc_mmio_regs();
  65
  66         if (config->s0ix_enable && config->cppmvric2_adsposcdis) {
  67                 /* Enable Audio DSP OSC qualification for S0ix */
  68                 reg32 = read32(pmcbase + CPPMVRIC2);
  69                 reg32 &= ~ADSPOSCDIS;
  70                 write32(pmcbase + CPPMVRIC2, reg32);
  71         }
  72
  73         pch_handle_sideband(config);
  74
  75         pmc_clear_pmcon_sts();
  76
  77         /*
  78          * Lock chipset memory registers to protect SMM.
  79          * When SkipMpInit=0, this is done by FSP.
  80          */
  81         if (!CONFIG(USE_INTEL_FSP_MP_INIT))
  82                 cpu_lt_lock_memory();
  83 }
  84
  85 static void soc_finalize(void *unused)
  86 {
  87         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  88
  89         pch_finalize();
  90         apm_control(APM_CNT_FINALIZE);
  91         if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) &&
  92                         CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC))
  93                 heci1_disable();
  94
  95         /* Indicate finalize step with post code */
  96         post_code(POSTCODE_OS_BOOT);
  97 }
  98
  99 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
 100 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);