src/soc/intel/cannonlake/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <console/console.h>
   5 #include <device/mmio.h>
   6 #include <device/device.h>
   7 #include <intelblocks/acpi.h>
   8 #include <intelblocks/pmc.h>
   9 #include <intelblocks/pmclib.h>
  10 #include <intelblocks/rtc.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/pm.h>
  13 #include <static.h>
  14
  15 #include "chip.h"
  16
  17 static void pm1_enable_pwrbtn_smi(void *unused)
  18 {
  19         /*
  20          * Enable power button SMI only before jumping to payload. This ensures
  21          * that:
  22          * 1. Power button SMI is enabled only after coreboot is done.
  23          * 2. On resume path, power button SMI is not enabled and thus avoids
  24          * any shutdowns because of power button presses due to power button
  25          * press in resume path.
  26          */
  27         pmc_update_pm1_enable(PWRBTN_EN);
  28 }
  29
  30 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
  31
  32 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
  33 {
  34         uint32_t reg;
  35         uint8_t *pmcbase = pmc_mmio_regs();
  36
  37         printk(BIOS_DEBUG, "%sabling Deep S%c\n",
  38                 enable ? "En" : "Dis", sx + '0');
  39         reg = read32(pmcbase + offset);
  40         if (enable)
  41                 reg |= mask;
  42         else
  43                 reg &= ~mask;
  44         write32(pmcbase + offset, reg);
  45 }
  46
  47 static void config_deep_s5(int on_ac, int on_dc)
  48 {
  49         /* Treat S4 the same as S5. */
  50         config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
  51         config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
  52         config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
  53         config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
  54 }
  55
  56 static void config_deep_s3(int on_ac, int on_dc)
  57 {
  58         config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
  59         config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
  60 }
  61
  62 static void config_deep_sx(uint32_t deepsx_config)
  63 {
  64         uint32_t reg;
  65         uint8_t *pmcbase = pmc_mmio_regs();
  66
  67         reg = read32(pmcbase + DSX_CFG);
  68         reg &= ~DSX_CFG_MASK;
  69         reg |= deepsx_config;
  70         write32(pmcbase + DSX_CFG, reg);
  71 }
  72
  73 static void soc_pmc_read_resources(struct device *dev)
  74 {
  75         struct resource *res;
  76
  77         /* Add the fixed MMIO resource */
  78         mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
  79
  80         /* Add the fixed I/O resource */
  81         res = new_resource(dev, 1);
  82         res->base = (resource_t)ACPI_BASE_ADDRESS;
  83         res->size = (resource_t)ACPI_BASE_SIZE;
  84         res->limit = res->base + res->size - 1;
  85         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  86 }
  87
  88 static void soc_pmc_enable(struct device *dev)
  89 {
  90         const config_t *config = config_of_soc();
  91
  92         rtc_init();
  93
  94         pmc_set_power_failure_state(true);
  95         pmc_gpe_init();
  96
  97         config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
  98         config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
  99         config_deep_sx(config->deep_sx_config);
 100 }
 101
 102 static void soc_pmc_init(struct device *dev)
 103 {
 104         /*
 105          * PMC initialization happens earlier for this SoC because FSP-Silicon
 106          * init hides PMC from PCI bus. However, pmc_set_acpi_mode, which
 107          * disables ACPI mode doesn't need to happen that early and can be
 108          * delayed till typical BS_DEV_INIT. This ensures that ACPI mode
 109          * disabling happens the same way for all SoCs and hence the ordering of
 110          * events is the same.
 111          *
 112          * This is important to ensure that the ordering does not break the
 113          * assumptions of any other drivers (e.g. ChromeEC) which could be
 114          * taking different actions based on disabling of ACPI (e.g. flushing of
 115          * all EC hostevent bits).
 116          *
 117          * Because the device is set as `hidden` in the devicetree, enumeration
 118          * is skipped, but the device callbacks are still called as if it were
 119          * found.
 120          */
 121         pmc_set_acpi_mode();
 122
 123         /*
 124          * Disable ACPI PM timer based on Kconfig
 125          *
 126          * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
 127          * Disabling ACPI PM timer also switches off TCO.
 128          */
 129         if (!CONFIG(USE_PM_ACPI_TIMER))
 130                 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
 131 }
 132
 133 static void pmc_fill_ssdt(const struct device *dev)
 134 {
 135         if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
 136                 generate_acpi_power_engine();
 137 }
 138
 139 /*
 140  * `pmc_final` function is native implementation of equivalent events performed by
 141  * each FSP NotifyPhase() API invocations.
 142  *
 143  *
 144  * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
 145  *
 146  * Perform the PMCON status bit clear operation from `.final`
 147  * to cover any such chances where later boot stage requested a global
 148  * reset and PMCON status bit remains set.
 149  */
 150 static void pmc_final(struct device *dev)
 151 {
 152         pmc_clear_pmcon_sts();
 153 }
 154
 155 struct device_operations pmc_ops = {
 156         .read_resources   = soc_pmc_read_resources,
 157         .set_resources    = noop_set_resources,
 158         .init             = soc_pmc_init,
 159         .enable           = soc_pmc_enable,
 160 #if CONFIG(HAVE_ACPI_TABLES)
 161         .acpi_fill_ssdt   = pmc_fill_ssdt,
 162 #endif
 163         .scan_bus         = scan_static_bus,
 164         .final            = pmc_final,
 165 };