src/soc/intel/pantherlake/bootblock/pcd.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/mmio.h>
   5 #include <device/device.h>
   6 #include <device/pci_ops.h>
   7 #include <intelblocks/fast_spi.h>
   8 #include <intelblocks/gspi.h>
   9 #include <intelblocks/lpc_lib.h>
  10 #include <intelblocks/p2sb.h>
  11 #include <intelblocks/pcr.h>
  12 #include <intelblocks/pmclib.h>
  13 #include <intelblocks/rtc.h>
  14 #include <intelblocks/systemagent.h>
  15 #include <intelblocks/tco.h>
  16 #include <intelblocks/uart.h>
  17 #include <intelpch/espi.h>
  18 #include <soc/bootblock.h>
  19 #include <soc/iomap.h>
  20 #include <soc/p2sb.h>
  21 #include <soc/pci_devs.h>
  22 #include <soc/pcr_ids.h>
  23 #include <soc/pm.h>
  24 #include <soc/romstage.h>
  25
  26 #define PCR_PSF8_TO_SHDW_PMC_REG_BASE   0xA80
  27 #define  PCR_PSFX_TO_SHDW_BAR4          0x10
  28 #define  PCR_PSFX_TO_SHDW_PCIEN_IOEN    0x01
  29 #define  PCR_PSFX_T0_SHDW_PCIEN         0x1C
  30
  31 static void pcd_die_config_pwrmbase(void)
  32 {
  33         /*
  34          * Assign Resources to PWRMBASE
  35          * Clear BIT 1-2  Command Register
  36          */
  37         pci_and_config16(PCI_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
  38
  39         /* Program PWRM Base */
  40         pci_write_config32(PCI_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
  41
  42         /* Enable Bus Master and MMIO Space */
  43         pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
  44
  45         /* Enable PWRM in PMC */
  46         setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
  47 }
  48
  49 static void pcd_die_early_iorange_init(void)
  50 {
  51         uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
  52                 LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
  53
  54         /* IO Decode Range */
  55         if (CONFIG(DRIVERS_UART_8250IO))
  56                 lpc_io_setup_comm_a_b();
  57
  58         /* IO Decode Enable */
  59         lpc_enable_fixed_io_ranges(io_enables);
  60
  61         /* Program generic IO Decode Range */
  62         pch_enable_lpc();
  63 }
  64
  65 static void pcd_die_early_ip_init(void)
  66 {
  67         /*
  68          * Perform P2SB configuration before any another controller initialization as the
  69          * controller might want to perform PCR settings.
  70          */
  71         p2sb_enable_bar();
  72         ioe_p2sb_enable_bar();
  73         p2sb_configure_hpet();
  74
  75         fast_spi_early_init(SPI_BASE_ADDRESS);
  76         gspi_early_bar_init();
  77
  78         /*
  79          * Enabling PCD PMC PWRM Base for accessing
  80          * Global Reset Cause Register.
  81          */
  82         pcd_die_config_pwrmbase();
  83 }
  84
  85 static void pcd_die_early_sa_init(void)
  86 {
  87         const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
  88                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  89         };
  90
  91         bootblock_systemagent_early_init();
  92
  93         /* Enable MCHBAR early, needed by IOC driver */
  94         sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources));
  95 }
  96
  97 void bootblock_pcd_die_early_init(void)
  98 {
  99         /*
 100          * Ensure performing SA related programming including MCHBAR prior to accessing
 101          * IOC driver.
 102          */
 103         pcd_die_early_sa_init();
 104
 105         pcd_die_early_ip_init();
 106
 107         fast_spi_cache_bios_region();
 108         pcd_die_early_iorange_init();
 109         if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 110                 uart_bootblock_init();
 111 }
 112
 113 static void pcd_die_config_acpibase(void)
 114 {
 115         uint32_t pmc_reg_value;
 116         uint32_t pmc_base_reg = PCR_PSF8_TO_SHDW_PMC_REG_BASE;
 117
 118         pmc_reg_value = pcr_read32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
 119
 120         if (pmc_reg_value == 0xffffffff) {
 121                 printk(BIOS_WARNING, "PCR_PSFX_TO_SHDW_BAR4 has not been programmed.\n");
 122                 return;
 123         } else {
 124                 /* Disable Io Space before changing the address */
 125                 pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
 126                                 ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
 127                 /* Program ABASE in PSF8 PMC space BAR4*/
 128                 pcr_write32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
 129                                 ACPI_BASE_ADDRESS);
 130                 /* Enable IO Space */
 131                 pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
 132                                 ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
 133         }
 134 }
 135
 136 void bootblock_pcd_die_init(void)
 137 {
 138         /*
 139          * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
 140          * GPE0_STS, GPE0_EN registers.
 141          */
 142         pcd_die_config_acpibase();
 143
 144         /* Set up GPE configuration */
 145         pmc_gpe_init();
 146
 147         enable_rtc_upper_bank();
 148
 149         /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
 150         tco_configure();
 151 }