src/soc/intel/skylake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <commonlib/console/post_codes.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/mp.h>
   7 #include <cpu/x86/smm.h>
   8 #include <device/mmio.h>
   9 #include <device/pci.h>
  10 #include <device/pci_ops.h>
  11 #include <intelblocks/cpulib.h>
  12 #include <intelblocks/cse.h>
  13 #include <intelblocks/lpc_lib.h>
  14 #include <intelblocks/p2sb.h>
  15 #include <intelblocks/pcr.h>
  16 #include <intelblocks/pmclib.h>
  17 #include <intelblocks/tco.h>
  18 #include <intelblocks/thermal.h>
  19 #include <soc/me.h>
  20 #include <soc/p2sb.h>
  21 #include <soc/pci_devs.h>
  22 #include <soc/pcr_ids.h>
  23 #include <soc/pm.h>
  24 #include <soc/smbus.h>
  25 #include <soc/systemagent.h>
  26 #include <spi-generic.h>
  27
  28 #include "chip.h"
  29
  30 #define PSF_BASE_ADDRESS        0xA00
  31 #define PCR_PSFX_T0_SHDW_PCIEN  0x1C
  32 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS   (1 << 8)
  33
  34 void soc_disable_heci1_using_pcr(void)
  35 {
  36         /* unhide p2sb device */
  37         p2sb_unhide();
  38
  39         /* disable heci */
  40         pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
  41                 PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
  42
  43         p2sb_disable_sideband_access();
  44 }
  45
  46 static void pch_finalize_script(struct device *dev)
  47 {
  48         tco_lockdown();
  49
  50         /* Display me status before we hide it */
  51         intel_me_status();
  52
  53         /*
  54          * Set low maximum temp value used for dynamic thermal sensor
  55          * shutdown consideration.
  56          *
  57          * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
  58          * thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
  59          */
  60         pch_thermal_configuration();
  61
  62         /* we should disable Heci1 based on the config */
  63         if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
  64                 heci1_disable();
  65
  66         /* Hide p2sb device as the OS must not change BAR0. */
  67         p2sb_hide();
  68
  69         pmc_clear_pmcon_sts();
  70 }
  71
  72 static void soc_lockdown(struct device *dev)
  73 {
  74         struct soc_intel_skylake_config *config;
  75         u8 reg8;
  76
  77         config = config_of(dev);
  78
  79         /* Global SMI Lock */
  80         if (config->LockDownConfigGlobalSmi == 0) {
  81                 reg8 = pci_read_config8(dev, GEN_PMCON_A);
  82                 reg8 |= SMI_LOCK;
  83                 pci_write_config8(dev, GEN_PMCON_A, reg8);
  84         }
  85
  86         /*
  87          * Lock chipset memory registers to protect SMM.
  88          * When SkipMpInit=0, this is done by FSP.
  89          */
  90         if (!CONFIG(USE_INTEL_FSP_MP_INIT))
  91                 cpu_lt_lock_memory();
  92 }
  93
  94 static void soc_finalize(void *unused)
  95 {
  96         struct device *dev;
  97
  98         dev = PCH_DEV_PMC;
  99
 100         /* Check if PMC is enabled, else return */
 101         if (dev == NULL)
 102                 return;
 103
 104         printk(BIOS_DEBUG, "Finalizing chipset.\n");
 105
 106         pch_finalize_script(dev);
 107
 108         soc_lockdown(dev);
 109         apm_control(APM_CNT_FINALIZE);
 110
 111         /* Indicate finalize step with post code */
 112         post_code(POSTCODE_OS_BOOT);
 113 }
 114
 115 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
 116 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);