src/soc/intel/skylake/graphics.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <commonlib/helpers.h>
   4 #include <device/mmio.h>
   5 #include <device/pci_rom.h>
   6 #include <device/resource.h>
   7 #include <drivers/intel/gma/i915.h>
   8 #include <drivers/intel/gma/i915_reg.h>
   9 #include <intelblocks/graphics.h>
  10 #include <soc/ramstage.h>
  11 #include <soc/systemagent.h>
  12 #include <types.h>
  13
  14 void graphics_soc_panel_init(struct device *dev)
  15 {
  16         struct soc_intel_skylake_config *conf = config_of(dev);
  17         const struct i915_gpu_panel_config *panel_cfg;
  18         struct resource *mmio_res;
  19         uint8_t *base;
  20         u32 reg32;
  21
  22         if (!conf)
  23                 return;
  24
  25         panel_cfg = &conf->panel_cfg;
  26
  27         mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
  28         if (!mmio_res || !mmio_res->base)
  29                 return;
  30         base = (void *)(uintptr_t)mmio_res->base;
  31
  32         reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
  33         reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
  34         write32(base + PCH_PP_ON_DELAYS, reg32);
  35
  36         reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
  37         reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
  38         write32(base + PCH_PP_OFF_DELAYS, reg32);
  39
  40         reg32 = read32(base + PCH_PP_DIVISOR);
  41         reg32 &= ~0x1f;
  42         reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f;
  43         write32(base + PCH_PP_DIVISOR, reg32);
  44
  45         /* So far all devices seem to use the PCH PWM function.
  46            The CPU PWM registers are all zero after reset.      */
  47         if (panel_cfg->backlight_pwm_hz) {
  48                 /* Reference clock is 24MHz. We can choose either a 16
  49                    or a 128 step increment. Use 16 if we would have less
  50                    than 100 steps otherwise. */
  51                 const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
  52                 unsigned int pwm_increment, pwm_period;
  53                 u32 south_chicken1;
  54
  55                 south_chicken1 = read32(base + SOUTH_CHICKEN1);
  56                 if (panel_cfg->backlight_pwm_hz > hz_limit) {
  57                         pwm_increment = 16;
  58                         south_chicken1 &= ~1;
  59                 } else {
  60                         pwm_increment = 128;
  61                         south_chicken1 |= 1;
  62                 }
  63                 write32(base + SOUTH_CHICKEN1, south_chicken1);
  64
  65                 pwm_period = 24 * 1000 * 1000 / pwm_increment / panel_cfg->backlight_pwm_hz;
  66                 /* Start with a 50% duty cycle. */
  67                 write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
  68
  69                 write32(base + BLC_PWM_PCH_CTL1,
  70                         !!panel_cfg->backlight_polarity << 29 | BLM_PCH_PWM_ENABLE);
  71         }
  72 }
  73
  74 const struct i915_gpu_controller_info *
  75 intel_igd_get_controller_info(const struct device *device)
  76 {
  77         struct soc_intel_skylake_config *chip = device->chip_info;
  78         return &chip->gfx;
  79 }
  80
  81 /*
  82  * Some VGA option roms are used for several chipsets but they only have one PCI ID in their
  83  * header. If we encounter such an option rom, we need to do the mapping ourselves.
  84  */
  85 u32 map_oprom_vendev(u32 vendev)
  86 {
  87         u32 new_vendev = vendev;
  88
  89         switch (vendev) {
  90         case 0x80865916: /* PCI_DID_INTEL_KBL_GT2_SULTM */
  91         case 0x80865917: /* PCI_DID_INTEL_KBL_GT2_SULTMR */
  92                 new_vendev = SA_IGD_OPROM_VENDEV;
  93                 break;
  94         }
  95
  96         return new_vendev;
  97 }