src/soc/intel/skylake/me.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pci_ops.h>
   4 #include <bootstate.h>
   5 #include <commonlib/helpers.h>
   6 #include <console/console.h>
   7 #include <device/pci.h>
   8 #include <intelblocks/cse.h>
   9 #include <soc/iomap.h>
  10 #include <soc/me.h>
  11 #include <soc/pci_devs.h>
  12
  13 /* HFSTS1[3:0] Current Working State Values */
  14 static const char *const me_cws_values[] = {
  15         [ME_HFS_CWS_RESET]      = "Reset",
  16         [ME_HFS_CWS_INIT]       = "Initializing",
  17         [ME_HFS_CWS_REC]        = "Recovery",
  18         [3]                     = "Unknown (3)",
  19         [4]                     = "Unknown (4)",
  20         [ME_HFS_CWS_NORMAL]     = "Normal",
  21         [ME_HFS_CWS_WAIT]       = "Platform Disable Wait",
  22         [ME_HFS_CWS_TRANS]      = "OP State Transition",
  23         [ME_HFS_CWS_INVALID]    = "Invalid CPU Plugged In",
  24         [9]                     = "Unknown (9)",
  25         [10]                    = "Unknown (10)",
  26         [11]                    = "Unknown (11)",
  27         [12]                    = "Unknown (12)",
  28         [13]                    = "Unknown (13)",
  29         [14]                    = "Unknown (14)",
  30         [15]                    = "Unknown (15)",
  31 };
  32
  33 /* HFSTS1[8:6] Current Operation State Values */
  34 static const char *const me_opstate_values[] = {
  35         [ME_HFS_STATE_PREBOOT]  = "Preboot",
  36         [ME_HFS_STATE_M0_UMA]   = "M0 with UMA",
  37         [ME_HFS_STATE_M3]       = "M3 without UMA",
  38         [ME_HFS_STATE_M0]       = "M0 without UMA",
  39         [ME_HFS_STATE_BRINGUP]  = "Bring up",
  40         [ME_HFS_STATE_ERROR]    = "M0 without UMA but with error"
  41 };
  42
  43 /* HFSTS1[19:16] Current Operation Mode Values */
  44 static const char *const me_opmode_values[] = {
  45         [ME_HFS_MODE_NORMAL]    = "Normal",
  46         [ME_HFS_MODE_DEBUG]     = "Debug",
  47         [ME_HFS_MODE_DIS]       = "Soft Temporary Disable",
  48         [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
  49         [ME_HFS_MODE_OVER_MEI]  = "Security Override via MEI Message"
  50 };
  51
  52 /* HFSTS1[15:12] Error Code Values */
  53 static const char *const me_error_values[] = {
  54         [ME_HFS_ERROR_NONE]     = "No Error",
  55         [ME_HFS_ERROR_UNCAT]    = "Uncategorized Failure",
  56         [ME_HFS_ERROR_IMAGE]    = "Image Failure",
  57         [ME_HFS_ERROR_DEBUG]    = "Debug Failure"
  58 };
  59
  60 /* HFSTS2[31:28] ME Progress Code */
  61 static const char *const me_progress_values[] = {
  62         [ME_HFS2_PHASE_ROM]             = "ROM Phase",
  63         [1]                             = "Unknown (1)",
  64         [ME_HFS2_PHASE_UKERNEL]         = "uKernel Phase",
  65         [ME_HFS2_PHASE_BUP]             = "BUP Phase",
  66         [4]                             = "Unknown (4)",
  67         [5]                             = "Unknown (5)",
  68         [ME_HFS2_PHASE_HOST_COMM]       = "Host Communication",
  69         [7]                             = "Unknown (7)",
  70         [8]                             = "Unknown (8)"
  71 };
  72
  73 /* HFSTS2[27:24] Power Management Event */
  74 static const char *const me_pmevent_values[] = {
  75         [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] =
  76         "Clean Moff->Mx wake",
  77         [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] =
  78         "Moff->Mx wake after an error",
  79         [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] =
  80         "Clean global reset",
  81         [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] =
  82         "Global reset after an error",
  83         [ME_HFS2_PMEVENT_CLEAN_ME_RESET] =
  84         "Clean Intel ME reset",
  85         [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] =
  86         "Intel ME reset due to exception",
  87         [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] =
  88         "Pseudo-global reset",
  89         [ME_HFS2_PMEVENT_CM0_CM3] =
  90         "CM0->CM3",
  91         [ME_HFS2_PMEVENT_CM3_CM0] =
  92         "CM3->CM0",
  93         [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] =
  94         "Non-power cycle reset",
  95         [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] =
  96         "Power cycle reset through M3",
  97         [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] =
  98         "Power cycle reset through Moff",
  99         [ME_HFS2_PMEVENT_CMX_CMOFF] =
 100         "Cx/Mx->Cx/Moff",
 101         [ME_HFS2_PMEVENT_CM0_CM0PG] =
 102         "CM0->CM0PG",
 103         [ME_HFS2_PMEVENT_CM3_CM3PG] =
 104         "CM3->CM3PG",
 105         [ME_HFS2_PMEVENT_CM0PG_CM0] =
 106         "CM0PG->CM0"
 107
 108 };
 109
 110 /* Progress Code 0 states */
 111 static const char *const me_progress_rom_values[] = {
 112         [ME_HFS2_STATE_ROM_BEGIN]       = "BEGIN",
 113         [ME_HFS2_STATE_ROM_DISABLE]     = "DISABLE"
 114 };
 115
 116 /* Progress Code 1 states */
 117 static const char *const me_progress_bup_values[] = {
 118         [ME_HFS2_STATE_BUP_INIT] =
 119         "Initialization starts",
 120         [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] =
 121         "Disable the host wake event",
 122         [ME_HFS2_STATE_BUP_CG_ENABLE] =
 123         "Enabling CG for cset",
 124         [ME_HFS2_STATE_BUP_PM_HND_EN] =
 125         "Enabling PM handshaking",
 126         [ME_HFS2_STATE_BUP_FLOW_DET] =
 127         "Flow determination start process",
 128         [ME_HFS2_STATE_BUP_PMC_PATCHING] =
 129         "PMC Patching process",
 130         [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] =
 131         "Get VSCC params",
 132         [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] =
 133         "Set VSCC params",
 134         [ME_HFS2_STATE_BUP_VSCC_ERR] =
 135         "Error reading/matching the VSCC table in the descriptor",
 136         [ME_HFS2_STATE_BUP_EFSS_INIT] =
 137         "Initialize EFFS",
 138         [ME_HFS2_STATE_BUP_CHECK_STRAP] =
 139         "Check to see if straps say ME DISABLED",
 140         [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] =
 141         "Timeout waiting for PWROK",
 142         [ME_HFS2_STATE_BUP_STRAP_DIS] =
 143         "EFFS says ME disabled",
 144         [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] =
 145         "Possibly handle BUP manufacturing override strap",
 146         [ME_HFS2_STATE_BUP_M3] =
 147         "Bringup in M3",
 148         [ME_HFS2_STATE_BUP_M0] =
 149         "Bringup in M0",
 150         [ME_HFS2_STATE_BUP_FLOW_DET_ERR] =
 151         "Flow detection error",
 152         [ME_HFS2_STATE_BUP_M3_CLK_ERR] =
 153         "M3 clock switching error",
 154         [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] =
 155         "Host error - CPU reset timeout, DID timeout, memory missing",
 156         [ME_HFS2_STATE_BUP_M3_KERN_LOAD] =
 157         "M3 kernel load",
 158         [ME_HFS2_STATE_BUP_T32_MISSING] =
 159         "T34 missing - cannot program ICC",
 160         [ME_HFS2_STATE_BUP_WAIT_DID] =
 161         "Waiting for DID BIOS message",
 162         [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] =
 163         "Waiting for DID BIOS message failure",
 164         [ME_HFS2_STATE_BUP_DID_NO_FAIL] =
 165         "DID reported no error",
 166         [ME_HFS2_STATE_BUP_ENABLE_UMA] =
 167         "Enabling UMA",
 168         [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] =
 169         "Enabling UMA error",
 170         [ME_HFS2_STATE_BUP_SEND_DID_ACK] =
 171         "Sending DID Ack to BIOS",
 172         [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] =
 173         "Sending DID Ack to BIOS error",
 174         [ME_HFS2_STATE_BUP_M0_CLK] =
 175         "Switching clocks in M0",
 176         [ME_HFS2_STATE_BUP_M0_CLK_ERR] =
 177         "Switching clocks in M0 error",
 178         [ME_HFS2_STATE_BUP_TEMP_DIS] =
 179         "ME in temp disable",
 180         [ME_HFS2_STATE_BUP_M0_KERN_LOAD] =
 181         "M0 kernel load",
 182 };
 183
 184 void intel_me_status(void)
 185 {
 186         union me_hfsts1 hfs1;
 187         union me_hfsts2 hfs2;
 188         union me_hfsts3 hfs3;
 189         union me_hfsts6 hfs6;
 190
 191         if (!is_cse_enabled())
 192                 return;
 193
 194         hfs1.data = me_read_config32(PCI_ME_HFSTS1);
 195         hfs2.data = me_read_config32(PCI_ME_HFSTS2);
 196         hfs3.data = me_read_config32(PCI_ME_HFSTS3);
 197         hfs6.data = me_read_config32(PCI_ME_HFSTS6);
 198
 199         printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n",
 200                 hfs1.data);
 201         printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n",
 202                 hfs2.data);
 203         printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n",
 204                 hfs3.data);
 205         printk(BIOS_DEBUG, "ME: Host Firmware Status Register 4 : 0x%08X\n",
 206                 me_read_config32(PCI_ME_HFSTS4));
 207         printk(BIOS_DEBUG, "ME: Host Firmware Status Register 5 : 0x%08X\n",
 208                 me_read_config32(PCI_ME_HFSTS5));
 209         printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n",
 210                 hfs6.data);
 211         /* Check Current States */
 212         printk(BIOS_DEBUG, "ME: FW Partition Table      : %s\n",
 213                hfs1.fields.fpt_bad ? "BAD" : "OK");
 214         printk(BIOS_DEBUG, "ME: Bringup Loader Failure  : %s\n",
 215                hfs1.fields.ft_bup_ld_flr ? "YES" : "NO");
 216         printk(BIOS_DEBUG, "ME: Firmware Init Complete  : %s\n",
 217                hfs1.fields.fw_init_complete ? "YES" : "NO");
 218         printk(BIOS_DEBUG, "ME: Manufacturing Mode      : %s\n",
 219                hfs1.fields.mfg_mode ? "YES" : "NO");
 220         printk(BIOS_DEBUG, "ME: Boot Options Present    : %s\n",
 221                hfs1.fields.boot_options_present ? "YES" : "NO");
 222         printk(BIOS_DEBUG, "ME: Update In Progress      : %s\n",
 223                hfs1.fields.update_in_progress ? "YES" : "NO");
 224         printk(BIOS_DEBUG, "ME: D3 Support              : %s\n",
 225                hfs1.fields.d3_support_valid ? "YES" : "NO");
 226         printk(BIOS_DEBUG, "ME: D0i3 Support            : %s\n",
 227                hfs1.fields.d0i3_support_valid ? "YES" : "NO");
 228         printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n",
 229                hfs2.fields.low_power_state ? "YES" : "NO");
 230         printk(BIOS_DEBUG, "ME: CPU Replaced            : %s\n",
 231                hfs2.fields.cpu_replaced_sts  ? "YES" : "NO");
 232         printk(BIOS_DEBUG, "ME: CPU Replacement Valid   : %s\n",
 233                hfs2.fields.cpu_replaced_valid ? "YES" : "NO");
 234         printk(BIOS_DEBUG, "ME: Current Working State   : %s\n",
 235                me_cws_values[hfs1.fields.working_state]);
 236         printk(BIOS_DEBUG, "ME: Current Operation State : %s\n",
 237                me_opstate_values[hfs1.fields.operation_state]);
 238         printk(BIOS_DEBUG, "ME: Current Operation Mode  : %s\n",
 239                me_opmode_values[hfs1.fields.operation_mode]);
 240         printk(BIOS_DEBUG, "ME: Error Code              : %s\n",
 241                me_error_values[hfs1.fields.error_code]);
 242         printk(BIOS_DEBUG, "ME: Progress Phase          : %s\n",
 243                me_progress_values[hfs2.fields.progress_code]);
 244         printk(BIOS_DEBUG, "ME: Power Management Event  : %s\n",
 245                me_pmevent_values[hfs2.fields.current_pmevent]);
 246
 247         printk(BIOS_DEBUG, "ME: Progress Phase State    : ");
 248         switch (hfs2.fields.progress_code) {
 249         case ME_HFS2_PHASE_ROM:         /* ROM Phase */
 250                 if (hfs2.fields.current_state
 251                         < ARRAY_SIZE(me_progress_rom_values)
 252                     && me_progress_rom_values[hfs2.fields.current_state])
 253                         printk(BIOS_DEBUG, "%s",
 254                                me_progress_rom_values[
 255                                                 hfs2.fields.current_state]);
 256                 else
 257                         printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state);
 258                 break;
 259
 260         case ME_HFS2_PHASE_UKERNEL:     /* uKernel Phase */
 261                 printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state);
 262                 break;
 263
 264         case ME_HFS2_PHASE_BUP:         /* Bringup Phase */
 265                 if (hfs2.fields.current_state
 266                         < ARRAY_SIZE(me_progress_bup_values)
 267                     && me_progress_bup_values[hfs2.fields.current_state])
 268                         printk(BIOS_DEBUG, "%s",
 269                                 me_progress_bup_values[
 270                                         hfs2.fields.current_state]);
 271                 else
 272                         printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state);
 273                 break;
 274
 275         case ME_HFS2_PHASE_HOST_COMM:   /* Host Communication Phase */
 276                 if (!hfs2.fields.current_state)
 277                         printk(BIOS_DEBUG, "Host communication established");
 278                 else
 279                         printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state);
 280                 break;
 281
 282         default:
 283                 printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x",
 284                        hfs2.fields.progress_code, hfs2.fields.current_state);
 285         }
 286         printk(BIOS_DEBUG, "\n");
 287
 288         /* Power Down Mitigation Status */
 289         printk(BIOS_DEBUG, "ME: Power Down Mitigation   : %s\n",
 290                hfs3.fields.power_down_mitigation ? "YES" : "NO");
 291
 292         if (hfs3.fields.power_down_mitigation) {
 293                 printk(BIOS_INFO, "ME: PD Mitigation State     : ");
 294                 if (hfs3.fields.encrypt_key_override == 1 &&
 295                     hfs3.fields.encrypt_key_check == 0 &&
 296                     hfs3.fields.pch_config_change == 0)
 297                         printk(BIOS_INFO, "Normal Operation");
 298                 else if (hfs3.fields.encrypt_key_override == 1 &&
 299                          hfs3.fields.encrypt_key_check == 1 &&
 300                          hfs3.fields.pch_config_change == 0)
 301                         printk(BIOS_INFO, "Issue Detected and Recovered");
 302                 else
 303                         printk(BIOS_INFO, "Issue Detected but not Recovered");
 304                 printk(BIOS_INFO, "\n");
 305
 306                 printk(BIOS_DEBUG, "ME: Encryption Key Override : %s\n",
 307                        hfs3.fields.encrypt_key_override ? "Workaround Applied" :
 308                        "Unable to override");
 309                 printk(BIOS_DEBUG, "ME: Encryption Key Check    : %s\n",
 310                        hfs3.fields.encrypt_key_check ? "FAIL" : "PASS");
 311                 printk(BIOS_DEBUG, "ME: PCH Configuration Info  : %s\n",
 312                        hfs3.fields.pch_config_change ? "Changed" : "No Change");
 313         }
 314
 315         printk(BIOS_DEBUG, "ME: Firmware SKU            : ");
 316         switch (hfs3.fields.fw_sku) {
 317         case ME_HFS3_FW_SKU_CONSUMER:
 318                 printk(BIOS_DEBUG, "Consumer\n");
 319                 break;
 320         case ME_HFS3_FW_SKU_CORPORATE:
 321                 printk(BIOS_DEBUG, "Corporate\n");
 322                 break;
 323         default:
 324                 printk(BIOS_DEBUG, "Unknown (0x%x)\n",
 325                         hfs3.fields.fw_sku);
 326         }
 327
 328         printk(BIOS_DEBUG, "ME: FPF status              : ");
 329         switch (hfs6.fields.fpf_nvars) {
 330         case ME_HFS6_FPF_NOT_COMMITTED:
 331                 printk(BIOS_DEBUG, "unfused\n");
 332                 break;
 333         case ME_HFS6_FPF_ERROR:
 334                 printk(BIOS_DEBUG, "unknown\n");
 335                 break;
 336         default:
 337                 printk(BIOS_DEBUG, "fused\n");
 338         }
 339 }
 340
 341 int send_global_reset(void)
 342 {
 343         int status = 0;
 344         union me_hfsts1 hfs1;
 345
 346         if (!is_cse_enabled())
 347                 goto ret;
 348
 349         /* Check ME operating mode */
 350         hfs1.data = me_read_config32(PCI_ME_HFSTS1);
 351         if (hfs1.fields.operation_mode)
 352                 goto ret;
 353
 354         /* ME should be in Normal Mode for this command */
 355         status = cse_request_global_reset();
 356 ret:
 357         return status;
 358 }
 359
 360 /*
 361  * This can't be put in intel_me_status because by the time control
 362  * reaches there, ME doesn't respond to GET_FW_VERSION command.
 363  */
 364 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL);