src/soc/intel/skylake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cpu/x86/msr.h>
   4 #include <delay.h>
   5 #include <device/device.h>
   6 #include <device/pci_ops.h>
   7 #include <intelblocks/power_limit.h>
   8 #include <intelblocks/systemagent.h>
   9 #include <option.h>
  10 #include <soc/cpu.h>
  11 #include <soc/iomap.h>
  12 #include <soc/msr.h>
  13 #include <soc/pci_devs.h>
  14 #include <soc/systemagent.h>
  15 #include <static.h>
  16 #include <types.h>
  17 #include "chip.h"
  18
  19 bool soc_vtd_enabled(void)
  20 {
  21         const unsigned int vtd = get_uint_option("vtd", 1);
  22         if (!vtd)
  23                 return false;
  24         struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
  25         return root_dev &&
  26                 !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
  27 }
  28
  29 /*
  30  * SoC implementation
  31  *
  32  * Add all known fixed memory ranges for Host Controller/Memory
  33  * controller.
  34  */
  35 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  36 {
  37         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  38                 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
  39                                 "PCIEXBAR" },
  40                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  41                 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
  42                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  43                 { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
  44                 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
  45         };
  46
  47         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  48                         ARRAY_SIZE(soc_fixed_resources));
  49
  50         if (soc_vtd_enabled()) {
  51                 if (is_devfn_enabled(SA_DEVFN_IGD))
  52                         sa_add_fixed_mmio_resources(dev, index,
  53                                         &soc_gfxvt_mmio_descriptor, 1);
  54
  55                 sa_add_fixed_mmio_resources(dev, index,
  56                                 &soc_vtvc0_mmio_descriptor, 1);
  57         }
  58 }
  59
  60 /*
  61  * SoC implementation
  62  *
  63  * Perform System Agent Initialization during Ramstage phase.
  64  */
  65 void soc_systemagent_init(struct device *dev)
  66 {
  67         struct soc_power_limits_config *soc_config;
  68         config_t *config;
  69
  70         /* Enable Power Aware Interrupt Routing */
  71         enable_power_aware_intr();
  72
  73         /* Enable BIOS Reset CPL */
  74         enable_bios_reset_cpl();
  75
  76         /* Configure turbo power limits 1ms after reset complete bit */
  77         mdelay(1);
  78         config = config_of_soc();
  79         soc_config = &config->power_limits_config;
  80         set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
  81 }
  82
  83 int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
  84         uint64_t *prmrr_mask)
  85 {
  86         msr_t msr;
  87         msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
  88         *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
  89         msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
  90         *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
  91         return 0;
  92 }
  93
  94 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
  95 {
  96         switch (capid0_a_ddrsz) {
  97         case 1:
  98                 return 8192;
  99         case 2:
 100                 return 4096;
 101         case 3:
 102                 return 2048;
 103         default:
 104                 return 32768;
 105         }
 106 }