src/soc/intel/tigerlake/cpu.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Tiger Lake Processor CPU Datasheet
   5  * Document number: 575683
   6  * Chapter number: 15
   7  */
   8
   9 #include <device/pci.h>
  10 #include <cpu/x86/mp.h>
  11 #include <cpu/x86/msr.h>
  12 #include <cpu/intel/smm_reloc.h>
  13 #include <cpu/intel/turbo.h>
  14 #include <cpu/intel/common/common.h>
  15 #include <fsp/api.h>
  16 #include <intelblocks/cpulib.h>
  17 #include <intelblocks/mp_init.h>
  18 #include <intelblocks/msr.h>
  19 #include <soc/cpu.h>
  20 #include <soc/msr.h>
  21 #include <soc/pci_devs.h>
  22 #include <soc/soc_chip.h>
  23 #include <static.h>
  24 #include <types.h>
  25
  26 bool cpu_soc_is_in_untrusted_mode(void)
  27 {
  28         msr_t msr;
  29
  30         msr = rdmsr(MSR_BIOS_DONE);
  31         return !!(msr.lo & ENABLE_IA_UNTRUSTED);
  32 }
  33
  34 void cpu_soc_bios_done(void)
  35 {
  36         msr_t msr;
  37
  38         msr = rdmsr(MSR_BIOS_DONE);
  39         msr.lo |= ENABLE_IA_UNTRUSTED;
  40         wrmsr(MSR_BIOS_DONE, msr);
  41 }
  42
  43 static void soc_fsp_load(void)
  44 {
  45         fsps_load();
  46 }
  47
  48 static void configure_misc(void)
  49 {
  50         msr_t msr;
  51
  52         config_t *conf = config_of_soc();
  53
  54         msr = rdmsr(IA32_MISC_ENABLE);
  55         msr.lo |= (1 << 0);     /* Fast String enable */
  56         msr.lo |= (1 << 3);     /* TM1/TM2/EMTTM enable */
  57         wrmsr(IA32_MISC_ENABLE, msr);
  58
  59         /* Set EIST status */
  60         cpu_set_eist(conf->eist_enable);
  61
  62         /* Disable Thermal interrupts */
  63         msr.lo = 0;
  64         msr.hi = 0;
  65         wrmsr(IA32_THERM_INTERRUPT, msr);
  66
  67         /* Enable package critical interrupt only */
  68         msr.lo = 1 << 4;
  69         msr.hi = 0;
  70         wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
  71
  72         /* Enable PROCHOT */
  73         msr = rdmsr(MSR_POWER_CTL);
  74         msr.lo |= (1 << 0);     /* Enable Bi-directional PROCHOT as an input */
  75         msr.lo |= (1 << 23);    /* Lock it */
  76         wrmsr(MSR_POWER_CTL, msr);
  77 }
  78
  79 /* All CPUs including BSP will run the following function. */
  80 void soc_core_init(struct device *cpu)
  81 {
  82         /* Clear out pending MCEs */
  83         /* TODO(adurbin): This should only be done on a cold boot. Also, some
  84          * of these banks are core vs package scope. For now every CPU clears
  85          * every bank. */
  86         mca_configure();
  87
  88         enable_lapic_tpr();
  89
  90         /* Configure Enhanced SpeedStep and Thermal Sensors */
  91         configure_misc();
  92
  93         enable_pm_timer_emulation();
  94
  95         /* Enable Direct Cache Access */
  96         configure_dca_cap();
  97
  98         /* Set energy policy */
  99         set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 100
 101         /* Enable Turbo */
 102         enable_turbo();
 103 }
 104
 105 static void per_cpu_smm_trigger(void)
 106 {
 107         /* Relocate the SMM handler. */
 108         smm_relocate();
 109 }
 110
 111 static void post_mp_init(void)
 112 {
 113         /* Set Max Ratio */
 114         cpu_set_max_ratio();
 115
 116         /*
 117          * 1. Now that all APs have been relocated as well as the BSP let SMIs
 118          * start flowing.
 119          * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
 120          * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
 121          */
 122         global_smi_enable_no_pwrbtn();
 123 }
 124
 125 static const struct mp_ops mp_ops = {
 126         /*
 127          * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
 128          * that are set prior to ramstage.
 129          * Real MTRRs programming are being done after resource allocation.
 130          */
 131         .pre_mp_init = soc_fsp_load,
 132         .get_cpu_count = get_cpu_count,
 133         .get_smm_info = smm_info,
 134         .get_microcode_info = get_microcode_info,
 135         .pre_mp_smm_init = smm_initialize,
 136         .per_cpu_smm_trigger = per_cpu_smm_trigger,
 137         .relocation_handler = smm_relocation_handler,
 138         .post_mp_init = post_mp_init,
 139 };
 140
 141 void mp_init_cpus(struct bus *cpu_bus)
 142 {
 143         /* TODO: Handle mp_init_with_smm failure? */
 144         mp_init_with_smm(cpu_bus, &mp_ops);
 145
 146         /* Thermal throttle activation offset */
 147         configure_tcc_thermal_target();
 148 }