src/soc/qualcomm/ipq806x/memlayout.ld

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <memlayout.h>
   4
   5 #include <arch/header.ld>
   6
   7 SECTIONS
   8 {
   9         REGION(rpm, 0x00020000,  160K, 8K)
  10         SRAM_START(0x2A000000)
  11         /* This includes bootblock image, can be reused after bootblock starts */
  12 /*      UBER_SBL(0x2A000000, 48K) */
  13 /*      DDR(0x2A000000, 48K) */
  14         BOOTBLOCK(0x2A00C000, 24K)
  15         OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K)
  16         VBOOT2_WORK(0x2A022000, 12K)
  17         PRERAM_CBMEM_CONSOLE(0x2A026000, 32K)
  18         TIMESTAMP(0x2A02E000, 1K)
  19
  20 /*      0x2e400..0x3F000  67 KB free */
  21
  22 /* Keep the below area reserved at all times, it is used by various QCA
  23    components as shared data
  24         QCA_SHARED_RAM(2A03F000, 4K)
  25 */
  26         STACK(0x2A040000, 16K)
  27         PRERAM_CBFS_CACHE(0x2A044000, 83K)
  28         CBFS_MCACHE(0x2A059000, 8K)
  29         FMAP_CACHE(0x2A05B000, 2K)
  30         TTB_SUBTABLES(0x2A05B800, 2K)
  31         TTB(0x2A05C000, 16K)
  32         SRAM_END(0x2A060000)
  33
  34         DRAM_START(0x40000000)
  35         RAMSTAGE(0x40640000, 2M)
  36         SYMBOL(memlayout_cbmem_top, 0x59F80000)
  37         POSTRAM_CBFS_CACHE(0x59F80000, 384K)
  38         DMA_COHERENT(0x5A000000, 2M)
  39 }