src/soc/samsung/exynos5420/clock_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* Clock setup for SMDK5420 board based on EXYNOS5 */
   4
   5 #include <device/mmio.h>
   6 #include <soc/clk.h>
   7 #include <soc/cpu.h>
   8 #include <soc/dp.h>
   9 #include <soc/dmc.h>
  10 #include <soc/setup.h>
  11
  12 void system_clock_init(void)
  13 {
  14         u32 val;
  15
  16         /* Turn on the MCT as early as possible. */
  17         exynos_mct->g_tcon |= (1 << 8);
  18
  19         /* PLL locktime */
  20         write32(&exynos_clock->apll_lock, APLL_LOCK_VAL);
  21         write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL);
  22         write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL);
  23         write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL);
  24         write32(&exynos_clock->dpll_lock, DPLL_LOCK_VAL);
  25         write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL);
  26         write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL);
  27         write32(&exynos_clock->ipll_lock, IPLL_LOCK_VAL);
  28         write32(&exynos_clock->spll_lock, SPLL_LOCK_VAL);
  29         write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL);
  30         write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL);
  31
  32         setbits32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK);
  33
  34         write32(&exynos_clock->clk_src_top6, 0);
  35
  36         write32(&exynos_clock->clk_src_cdrex, 0);
  37         write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL);
  38         write32(&exynos_clock->clk_div_cpu1, HPM_RATIO);
  39         write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL);
  40
  41         /* switch A15 clock source to OSC clock before changing APLL */
  42         clrbits32(&exynos_clock->clk_src_cpu, APLL_FOUT);
  43
  44         /* Set APLL */
  45         write32(&exynos_clock->apll_con1, APLL_CON1_VAL);
  46         val = set_pll(225, 3, 0);       /* FOUT=1800MHz */
  47         write32(&exynos_clock->apll_con0, val);
  48         while ((read32(&exynos_clock->apll_con0) & PLL_LOCKED) == 0)
  49                 ;
  50
  51         /* now it is safe to switch to APLL */
  52         setbits32(&exynos_clock->clk_src_cpu, APLL_FOUT);
  53
  54         write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL);
  55         write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL);
  56
  57         /* switch A7 clock source to OSC clock before changing KPLL */
  58         clrbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
  59
  60         /* Set KPLL*/
  61         write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL);
  62         val = set_pll(0x190, 0x4, 0x2);
  63         write32(&exynos_clock->kpll_con0, val);
  64         while ((read32(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0)
  65                 ;
  66
  67         /* now it is safe to switch to KPLL */
  68         setbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
  69
  70         /* Set MPLL */
  71         write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL);
  72         val = set_pll(0xc8, 0x3, 0x1);
  73         write32(&exynos_clock->mpll_con0, val);
  74         while ((read32(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0)
  75                 ;
  76
  77         /* Set DPLL */
  78         write32(&exynos_clock->dpll_con1, DPLL_CON1_VAL);
  79         val = set_pll(0x190, 0x4, 0x2);
  80         write32(&exynos_clock->dpll_con0, val);
  81         while ((read32(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0)
  82                 ;
  83
  84         /* Set EPLL */
  85         write32(&exynos_clock->epll_con2, EPLL_CON2_VAL);
  86         write32(&exynos_clock->epll_con1, EPLL_CON1_VAL);
  87         val = set_pll(0x64, 0x2, 0x1);
  88         write32(&exynos_clock->epll_con0, val);
  89         while ((read32(&exynos_clock->epll_con0) & PLL_LOCKED) == 0)
  90                 ;
  91
  92         /* Set CPLL */
  93         write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL);
  94         val = set_pll(0xde, 0x4, 0x1);
  95         write32(&exynos_clock->cpll_con0, val);
  96         while ((read32(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0)
  97                 ;
  98
  99         /* Set IPLL */
 100         write32(&exynos_clock->ipll_con1, IPLL_CON1_VAL);
 101         val = set_pll(0xB9, 0x3, 0x2);
 102         write32(&exynos_clock->ipll_con0, val);
 103         while ((read32(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0)
 104                 ;
 105
 106         /* Set VPLL */
 107         write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL);
 108         val = set_pll(0xd7, 0x3, 0x2);
 109         write32(&exynos_clock->vpll_con0, val);
 110         while ((read32(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0)
 111                 ;
 112
 113         /* Set BPLL */
 114         write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL);
 115         val = set_pll(0xc8, 0x3, 0x1);
 116         write32(&exynos_clock->bpll_con0, val);
 117         while ((read32(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0)
 118                 ;
 119
 120         /* Set SPLL */
 121         write32(&exynos_clock->spll_con1, SPLL_CON1_VAL);
 122         val = set_pll(200, 0x3, 0x2);   /* 400MHz */
 123         write32(&exynos_clock->spll_con0, val);
 124         while ((read32(&exynos_clock->spll_con0) & PLL_LOCKED) == 0)
 125                 ;
 126
 127         /* We use RPLL as the source for FIMD video stream clock */
 128         write32(&exynos_clock->rpll_con1, RPLL_CON1_VAL);
 129         write32(&exynos_clock->rpll_con2, RPLL_CON2_VAL);
 130         /* computed by gabe from first principles; u-boot is probably
 131          * wrong again
 132          */
 133         val = set_pll(0xa0, 0x3, 0x2);
 134         write32(&exynos_clock->rpll_con0, val);
 135         /* note: this is a meaningless exercise. The hardware lock
 136          * detection does not work. So this just spins for some
 137          * time and is done. NO indication of success should attach
 138          * to this or any other spin on a con0 value.
 139          */
 140         while ((read32(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0)
 141                 ;
 142
 143         write32(&exynos_clock->clk_div_cdrex0, CLK_DIV_CDREX0_VAL);
 144         write32(&exynos_clock->clk_div_cdrex1, CLK_DIV_CDREX1_VAL);
 145
 146         write32(&exynos_clock->clk_src_top0, CLK_SRC_TOP0_VAL);
 147         write32(&exynos_clock->clk_src_top1, CLK_SRC_TOP1_VAL);
 148         write32(&exynos_clock->clk_src_top2, CLK_SRC_TOP2_VAL);
 149         write32(&exynos_clock->clk_src_top7, CLK_SRC_TOP7_VAL);
 150
 151         write32(&exynos_clock->clk_div_top0, CLK_DIV_TOP0_VAL);
 152         write32(&exynos_clock->clk_div_top1, CLK_DIV_TOP1_VAL);
 153         write32(&exynos_clock->clk_div_top2, CLK_DIV_TOP2_VAL);
 154
 155         write32(&exynos_clock->clk_src_top10, 0);
 156         write32(&exynos_clock->clk_src_top11, 0);
 157         write32(&exynos_clock->clk_src_top12, 0);
 158
 159         write32(&exynos_clock->clk_src_top3, CLK_SRC_TOP3_VAL);
 160         write32(&exynos_clock->clk_src_top4, CLK_SRC_TOP4_VAL);
 161         write32(&exynos_clock->clk_src_top5, CLK_SRC_TOP5_VAL);
 162
 163         /* DISP1 BLK CLK SELECTION */
 164         write32(&exynos_clock->clk_src_disp10, CLK_SRC_DISP1_0_VAL);
 165         write32(&exynos_clock->clk_div_disp10, CLK_DIV_DISP1_0_VAL);
 166
 167         /* AUDIO BLK */
 168         write32(&exynos_clock->clk_src_mau, AUDIO0_SEL_EPLL);
 169         write32(&exynos_clock->clk_div_mau, DIV_MAU_VAL);
 170
 171         /* FSYS */
 172         write32(&exynos_clock->clk_src_fsys, CLK_SRC_FSYS0_VAL);
 173         write32(&exynos_clock->clk_div_fsys0, CLK_DIV_FSYS0_VAL);
 174         write32(&exynos_clock->clk_div_fsys1, CLK_DIV_FSYS1_VAL);
 175         write32(&exynos_clock->clk_div_fsys2, CLK_DIV_FSYS2_VAL);
 176
 177         write32(&exynos_clock->clk_src_isp, CLK_SRC_ISP_VAL);
 178         write32(&exynos_clock->clk_div_isp0, CLK_DIV_ISP0_VAL);
 179         write32(&exynos_clock->clk_div_isp1, CLK_DIV_ISP1_VAL);
 180
 181         write32(&exynos_clock->clk_src_peric0, CLK_SRC_PERIC0_VAL);
 182         write32(&exynos_clock->clk_src_peric1, CLK_SRC_PERIC1_VAL);
 183
 184         write32(&exynos_clock->clk_div_peric0, CLK_DIV_PERIC0_VAL);
 185         write32(&exynos_clock->clk_div_peric1, CLK_DIV_PERIC1_VAL);
 186         write32(&exynos_clock->clk_div_peric2, CLK_DIV_PERIC2_VAL);
 187         write32(&exynos_clock->clk_div_peric3, CLK_DIV_PERIC3_VAL);
 188         write32(&exynos_clock->clk_div_peric4, CLK_DIV_PERIC4_VAL);
 189
 190         write32(&exynos_clock->clk_div_cperi1, CLK_DIV_CPERI1_VAL);
 191
 192         write32(&exynos_clock->clkdiv2_ratio, CLK_DIV2_RATIO);
 193         write32(&exynos_clock->clkdiv4_ratio, CLK_DIV4_RATIO);
 194         write32(&exynos_clock->clk_div_g2d, CLK_DIV_G2D);
 195
 196         write32(&exynos_clock->clk_src_cpu, CLK_SRC_CPU_VAL);
 197         write32(&exynos_clock->clk_src_top6, CLK_SRC_TOP6_VAL);
 198         write32(&exynos_clock->clk_src_cdrex, CLK_SRC_CDREX_VAL);
 199         write32(&exynos_clock->clk_src_kfc, CLK_SRC_KFC_VAL);
 200 }
 201
 202 void clock_gate(void)
 203 {
 204         /* Not implemented for now. */
 205 }