src/soc/samsung/exynos5420/fimd.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <device/mmio.h>
   4 #include <console/console.h>
   5 #include <soc/clk.h>
   6 #include <soc/dp.h>
   7 #include <soc/fimd.h>
   8 #include <soc/periph.h>
   9 #include <soc/sysreg.h>
  10
  11 /* fairly useful debugging stuff. */
  12 #if 0
  13 static inline void fwadl(unsigned long l,void *v) {
  14         writel(l, v);
  15         printk(BIOS_SPEW, "W %p %p\n", v, (void *)l);
  16 }
  17 #define lwritel(a,b) fwadl((unsigned long)(a), (void *)(b))
  18
  19 static inline unsigned long fradl(void *v) {
  20         unsigned long l = readl(v);
  21         printk(BIOS_SPEW, "R %p %p\n", v, (void *)l);
  22         return l;
  23 }
  24
  25 #define lreadl(a) fradl((void *)(a))
  26
  27 #else
  28 #define lwritel(a,b) write32((void *)(b), (unsigned long)(a))
  29 #define lreadl(a) read32((void *)(a))
  30 #endif
  31
  32 /* not sure where we want this so ... */
  33 static unsigned long get_lcd_clk(void)
  34 {
  35         u32 pclk, sclk;
  36         unsigned int sel;
  37         unsigned int ratio;
  38
  39         /*
  40          * CLK_SRC_DISP10
  41          * CLKMUX_FIMD1 [4]
  42          * 0: SCLK_RPLL
  43          * 1: SCLK_SPLL
  44          */
  45         sel = lreadl(&exynos_clock->clk_src_disp10);
  46         sel &= (1 << 4);
  47
  48         if (sel){
  49                 sclk = get_pll_clk(SPLL);
  50         } else {
  51                 sclk = get_pll_clk(RPLL);
  52         }
  53
  54         /*
  55          * CLK_DIV_DISP10
  56          * FIMD1_RATIO [3:0]
  57          */
  58         ratio = lreadl(&exynos_clock->clk_div_disp10);
  59         ratio = ratio & 0xf;
  60
  61         pclk = sclk / (ratio + 1);
  62
  63         return pclk;
  64 }
  65
  66 static void exynos_fimd_set_dualrgb(vidinfo_t *vid, unsigned int enabled)
  67 {
  68         unsigned int cfg = 0;
  69         printk(BIOS_SPEW, "%s %s\n", __func__, enabled ? "enabled" : "not enabled");
  70         if (enabled) {
  71                 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
  72                         EXYNOS_DUALRGB_VDEN_EN_ENABLE;
  73
  74                 /* in case of Line Split mode, MAIN_CNT doesn't need to be set. */
  75                 cfg |= EXYNOS_DUALRGB_SUB_CNT(vid->vl_col / 2) |
  76                         EXYNOS_DUALRGB_MAIN_CNT(0);
  77         }
  78
  79         lwritel(cfg, &FIMD_CTRL->dualrgb);
  80 }
  81
  82 static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
  83 {
  84         unsigned int cfg = 0;
  85
  86         if (enabled){
  87                 cfg = EXYNOS_DP_CLK_ENABLE;
  88         }
  89
  90         lwritel(cfg, &FIMD_CTRL->dp_mie_clkcon);
  91 }
  92
  93 static void exynos_fimd_set_par(vidinfo_t *vid, unsigned int win_id)
  94 {
  95         unsigned int cfg = 0;
  96         printk(BIOS_SPEW, "%s %d\n", __func__, win_id);
  97         /* set window control */
  98         cfg = lreadl(&FIMD_CTRL->wincon0 +
  99                     EXYNOS_WINCON(win_id));
 100
 101         cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
 102                  EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
 103                  EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
 104                  EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
 105
 106         /* DATAPATH is DMA */
 107         cfg |= EXYNOS_WINCON_DATAPATH_DMA;
 108
 109         cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
 110
 111         /* dma burst is 16 */
 112         cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
 113
 114         cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
 115
 116         lwritel(cfg, &FIMD_CTRL->wincon0 +
 117                EXYNOS_WINCON(win_id));
 118
 119         /* set window position to x=0, y=0*/
 120         cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
 121         lwritel(cfg, &FIMD_CTRL->vidosd0a +
 122                EXYNOS_VIDOSD(win_id));
 123
 124         cfg = EXYNOS_VIDOSD_RIGHT_X(vid->vl_col - 1) |
 125                 EXYNOS_VIDOSD_BOTTOM_Y(vid->vl_row - 1) |
 126                 EXYNOS_VIDOSD_RIGHT_X_E(1) |
 127                 EXYNOS_VIDOSD_BOTTOM_Y_E(0);
 128
 129         lwritel(cfg, &FIMD_CTRL->vidosd0b +
 130                EXYNOS_VIDOSD(win_id));
 131         /* set window size for window0*/
 132         cfg = EXYNOS_VIDOSD_SIZE(vid->vl_col * vid->vl_row);
 133         lwritel(cfg, &FIMD_CTRL->vidosd0c +
 134                EXYNOS_VIDOSD(win_id));
 135 }
 136
 137 static void exynos_fimd_set_buffer_address(vidinfo_t *vid,
 138         void *screen_base, int win_id)
 139 {
 140         u32 start_addr, end_addr;
 141         printk(BIOS_SPEW, "%s %d\n", __func__, win_id);
 142         start_addr = (u32)screen_base;
 143         end_addr = start_addr + ((vid->vl_col * ((1<<vid->vl_bpix) / 8)) *
 144                                  vid->vl_row);
 145
 146         lwritel(start_addr, &FIMD_CTRL->vidw00add0b0 +
 147                EXYNOS_BUFFER_OFFSET(win_id));
 148         lwritel(end_addr, &FIMD_CTRL->vidw00add1b0 +
 149                EXYNOS_BUFFER_OFFSET(win_id));
 150 }
 151
 152 static void exynos_fimd_set_clock(vidinfo_t *vid)
 153 {
 154         unsigned int cfg = 0, div = 0, remainder = 0, remainder_div;
 155         unsigned long pixel_clock;
 156         unsigned long long src_clock;
 157         printk(BIOS_SPEW, "%s\n", __func__);
 158         if (vid->dual_lcd_enabled) {
 159                 pixel_clock = vid->vl_freq *
 160                         (vid->vl_hspw + vid->vl_hfpd +
 161                          vid->vl_hbpd + vid->vl_col / 2) *
 162                         (vid->vl_vspw + vid->vl_vfpd +
 163                          vid->vl_vbpd + vid->vl_row);
 164         } else if (vid->interface_mode == FIMD_CPU_INTERFACE) {
 165                 pixel_clock = vid->vl_freq *
 166                         vid->vl_width * vid->vl_height *
 167                         (vid->cs_setup + vid->wr_setup +
 168                          vid->wr_act + vid->wr_hold + 1);
 169         } else {
 170                 pixel_clock = vid->vl_freq *
 171                         (vid->vl_hspw + vid->vl_hfpd +
 172                          vid->vl_hbpd + vid->vl_col) *
 173                         (vid->vl_vspw + vid->vl_vfpd +
 174                          vid->vl_vbpd + vid->vl_row);
 175         }
 176         printk(BIOS_SPEW, "Pixel clock is %lx\n", pixel_clock);
 177
 178         cfg = lreadl(&FIMD_CTRL->vidcon0);
 179         cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
 180                  EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
 181                  EXYNOS_VIDCON0_CLKDIR_MASK);
 182         cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
 183                 EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
 184
 185         src_clock = (unsigned long long)get_lcd_clk();
 186
 187         /* get quotient and remainder. */
 188         remainder = src_clock % pixel_clock;
 189         src_clock /= pixel_clock;
 190
 191         div = src_clock;
 192
 193         remainder *= 10;
 194         remainder_div = remainder / pixel_clock;
 195
 196         /* round about one places of decimals. */
 197         if (remainder_div >= 5)
 198                 div++;
 199
 200         /* in case of dual lcd mode. */
 201         if (vid->dual_lcd_enabled)
 202                 div--;
 203
 204         cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
 205         lwritel(cfg, &FIMD_CTRL->vidcon0);
 206 }
 207
 208 void exynos_set_trigger(void)
 209 {
 210         unsigned int cfg = 0;
 211         printk(BIOS_SPEW, "%s\n", __func__);
 212         cfg = lreadl(&FIMD_CTRL->trigcon);
 213
 214         cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
 215
 216         lwritel(cfg, &FIMD_CTRL->trigcon);
 217 }
 218
 219 int exynos_is_i80_frame_done(void)
 220 {
 221         unsigned int cfg = 0;
 222         int status;
 223         printk(BIOS_SPEW, "%s\n", __func__);
 224         cfg = lreadl(&FIMD_CTRL->trigcon);
 225
 226         /* frame done func is valid only when TRIMODE[0] is set to 1. */
 227         status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
 228                 EXYNOS_I80STATUS_TRIG_DONE;
 229
 230         return status;
 231 }
 232
 233 static void exynos_fimd_lcd_on(void)
 234 {
 235         unsigned int cfg = 0;
 236
 237         printk(BIOS_SPEW, "%s\n", __func__);
 238         /* display on */
 239         cfg = lreadl(&FIMD_CTRL->vidcon0);
 240         cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
 241         lwritel(cfg, &FIMD_CTRL->vidcon0);
 242 }
 243
 244 static void exynos_fimd_window_on(unsigned int win_id)
 245 {
 246         unsigned int cfg = 0;
 247         printk(BIOS_SPEW, "%s %d\n", __func__, win_id);
 248         /* enable window */
 249         cfg = lreadl(&FIMD_CTRL->wincon0 +
 250                     EXYNOS_WINCON(win_id));
 251         cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
 252         lwritel(cfg, &FIMD_CTRL->wincon0 +
 253                EXYNOS_WINCON(win_id));
 254
 255         cfg = lreadl(&FIMD_CTRL->winshmap);
 256         cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
 257         lwritel(cfg, &FIMD_CTRL->winshmap);
 258         cfg = lreadl(&FIMD_CTRL->winshmap);
 259 }
 260
 261 void exynos_fimd_lcd_off(void)
 262 {
 263         unsigned int cfg = 0;
 264         printk(BIOS_SPEW, "%s\n", __func__);
 265
 266         cfg = lreadl(&FIMD_CTRL->vidcon0);
 267         cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
 268         lwritel(cfg, &FIMD_CTRL->vidcon0);
 269 }
 270
 271 void exynos_fimd_window_off(unsigned int win_id)
 272 {
 273         unsigned int cfg = 0;
 274         printk(BIOS_SPEW, "%s %d\n", __func__, win_id);
 275
 276         cfg = lreadl(&FIMD_CTRL->wincon0 +
 277                     EXYNOS_WINCON(win_id));
 278         cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
 279         lwritel(cfg, &FIMD_CTRL->wincon0 +
 280                EXYNOS_WINCON(win_id));
 281
 282         cfg = lreadl(&FIMD_CTRL->winshmap);
 283         cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
 284         lwritel(cfg, &FIMD_CTRL->winshmap);
 285 }
 286
 287 static void exynos5_set_system_display(void)
 288 {
 289         unsigned int cfg = 0;
 290
 291         /*
 292          * system register path set
 293          * 0: MIE/MDNIE
 294          * 1: FIMD Bypass
 295          */
 296         cfg = lreadl(&exynos_sysreg->disp1blk_cfg);
 297         cfg |= (1 << 15);
 298         lwritel(cfg, &exynos_sysreg->disp1blk_cfg);
 299 }
 300
 301 void exynos_fimd_lcd_init(vidinfo_t *vid)
 302 {
 303         unsigned int cfg = 0, rgb_mode;
 304         struct exynos_fb *fimd;
 305
 306         fimd = (void *)(FIMD_CTRL_ADDR + EXYNOS5_LCD_IF_BASE_OFFSET);
 307
 308         printk(BIOS_SPEW, "%s\n", __func__);
 309         exynos5_set_system_display();
 310
 311         rgb_mode = vid->rgb_mode;
 312
 313         if (vid->interface_mode == FIMD_RGB_INTERFACE) {
 314                 printk(BIOS_SPEW, "%s FIMD_RGB_INTERFACE\n", __func__);
 315
 316                 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
 317                 lwritel(cfg, &FIMD_CTRL->vidcon0);
 318
 319                 cfg = lreadl(&FIMD_CTRL->vidcon2);
 320                 cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
 321                         EXYNOS_VIDCON2_TVFORMATSEL_MASK |
 322                         EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
 323                 cfg |= EXYNOS_VIDCON2_WB_DISABLE;
 324                 lwritel(cfg, &FIMD_CTRL->vidcon2);
 325
 326                 /* set polarity */
 327                 cfg = 0;
 328                 if (!vid->vl_clkp)
 329                         cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
 330                 if (!vid->vl_hsp)
 331                         cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
 332                 if (!vid->vl_vsp)
 333                         cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
 334                 if (!vid->vl_dp)
 335                         cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
 336
 337                 lwritel(cfg, &fimd->vidcon1);
 338
 339                 /* set timing */
 340                 cfg = EXYNOS_VIDTCON0_VFPD(vid->vl_vfpd - 1);
 341                 cfg |= EXYNOS_VIDTCON0_VBPD(vid->vl_vbpd - 1);
 342                 cfg |= EXYNOS_VIDTCON0_VSPW(vid->vl_vspw - 1);
 343                 lwritel(cfg, &fimd->vidtcon0);
 344
 345                 cfg = EXYNOS_VIDTCON1_HFPD(vid->vl_hfpd - 1);
 346                 cfg |= EXYNOS_VIDTCON1_HBPD(vid->vl_hbpd - 1);
 347                 cfg |= EXYNOS_VIDTCON1_HSPW(vid->vl_hspw - 1);
 348
 349                 lwritel(cfg, &fimd->vidtcon1);
 350
 351                 /* set lcd size */
 352                 cfg = EXYNOS_VIDTCON2_HOZVAL(vid->vl_col - 1) |
 353                         EXYNOS_VIDTCON2_LINEVAL(vid->vl_row - 1) |
 354                         EXYNOS_VIDTCON2_HOZVAL_E(vid->vl_col - 1) |
 355                         EXYNOS_VIDTCON2_LINEVAL_E(vid->vl_row - 1);
 356
 357                 lwritel(cfg, &fimd->vidtcon2);
 358         }
 359
 360         /* set display mode */
 361         cfg = lreadl(&FIMD_CTRL->vidcon0);
 362         cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
 363         cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
 364         lwritel(cfg, &FIMD_CTRL->vidcon0);
 365
 366         /* set par */
 367         exynos_fimd_set_par(vid, vid->win_id);
 368
 369         /* set memory address */
 370         exynos_fimd_set_buffer_address(vid, vid->screen_base, vid->win_id);
 371
 372         /* set buffer size */
 373         cfg = EXYNOS_VIDADDR_PAGEWIDTH(vid->vl_col * (1<<vid->vl_bpix) / 8) |
 374                 EXYNOS_VIDADDR_PAGEWIDTH_E(vid->vl_col * (1<<vid->vl_bpix) / 8) |
 375                 EXYNOS_VIDADDR_OFFSIZE(0) |
 376                 EXYNOS_VIDADDR_OFFSIZE_E(0);
 377
 378         lwritel(cfg, &FIMD_CTRL->vidw00add2 +
 379                                         EXYNOS_BUFFER_SIZE(vid->win_id));
 380
 381         /* set clock */
 382         exynos_fimd_set_clock(vid);
 383
 384         /* set rgb mode to dual lcd. */
 385         exynos_fimd_set_dualrgb(vid, vid->dual_lcd_enabled);
 386
 387         /* display on */
 388         exynos_fimd_lcd_on();
 389
 390         /* window on */
 391         exynos_fimd_window_on(vid->win_id);
 392
 393         exynos_fimd_set_dp_clkcon(vid->dp_enabled);
 394         exynos5_set_system_display();
 395         printk(BIOS_SPEW, "%s: done\n", __func__);
 396 }
 397
 398 unsigned long exynos_fimd_calc_fbsize(vidinfo_t *vid)
 399 {
 400         printk(BIOS_SPEW, "%s\n", __func__);
 401         return vid->vl_col * vid->vl_row * ((1<<vid->vl_bpix) / 8);
 402 }
 403
 404 void exynos_fimd_lcd_disable(void)
 405 {
 406         int i;
 407         printk(BIOS_SPEW, "%s\n", __func__);
 408
 409         for (i = 0; i < 4; i++)
 410                 exynos_fimd_window_off(i);
 411 }