soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION
[coreboot2.git] / util / inteltool / gpio_groups.c
blob953a60ea102c5fdcd67256c6bc86a7526aa518e3
1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /* SPDX-License-Identifier: GPL-2.0-only */
4 #include <stdio.h>
5 #include <stdlib.h>
6 #include <stddef.h>
7 #include <stdint.h>
8 #include <assert.h>
9 #include <inttypes.h>
10 #include "inteltool.h"
11 #include "pcr.h"
13 #include "gpio_names/apollolake.h"
14 #include "gpio_names/cannonlake.h"
15 #include "gpio_names/cannonlake_lp.h"
16 #include "gpio_names/denverton.h"
17 #include "gpio_names/geminilake.h"
18 #include "gpio_names/icelake.h"
19 #include "gpio_names/lewisburg.h"
20 #include "gpio_names/emmitsburg.h"
21 #include "gpio_names/sunrise.h"
22 #include "gpio_names/tigerlake.h"
23 #include "gpio_names/alderlake_h.h"
24 #include "gpio_names/alderlake_p.h"
25 #include "gpio_names/elkhartlake.h"
26 #include "gpio_names/jasperlake.h"
28 #define SBBAR_SIZE (16 * MiB)
29 #define PCR_PORT_SIZE (64 * KiB)
31 static const char *decode_pad_mode(const struct gpio_group *const group,
32 const size_t pad, const uint32_t dw0)
34 const size_t pad_mode = dw0 >> 10 & 7;
35 const char *const pad_name =
36 group->pad_names[pad * group->func_count + pad_mode];
38 if (!pad_mode)
39 return pad_name[0] == '*' ? "*GPIO" : "GPIO";
40 else if (pad_mode < group->func_count)
41 return group->pad_names[pad * group->func_count + pad_mode];
42 else
43 return "RESERVED";
46 static void print_gpio_group(const uint8_t pid, size_t pad_cfg,
47 const struct gpio_group *const group,
48 size_t pad_stepping)
50 size_t p;
52 printf("%s\n", group->display);
54 for (p = 0; p < group->pad_count; ++p, pad_cfg += pad_stepping) {
55 const uint32_t dw0 = read_pcr32(pid, pad_cfg);
56 const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4);
57 const char *const pad_name =
58 group->pad_names[p * group->func_count];
60 printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg,
61 (uint64_t)dw1 << 32 | dw0,
62 pad_name[0] == '*' ? &pad_name[1] : pad_name,
63 decode_pad_mode(group, p, dw0));
67 static void print_gpio_community(const struct gpio_community *const community,
68 size_t pad_stepping)
70 size_t group, pad_count;
71 size_t pad_cfg; /* offset in bytes under this communities PCR port */
73 printf("%s\n\nPCR Port ID: 0x%06zx\n\n",
74 community->name, (size_t)community->pcr_port_id << 16);
76 for (group = 0, pad_count = 0; group < community->group_count; ++group)
77 pad_count += community->groups[group]->pad_count;
78 assert(pad_count * 8 <= PCR_PORT_SIZE - 0x10);
80 pad_cfg = read_pcr32(community->pcr_port_id, 0x0c);
81 if (pad_cfg + pad_count * 8 > PCR_PORT_SIZE) {
82 fprintf(stderr, "Bad Pad Base Address: 0x%08zx\n", pad_cfg);
83 return;
86 for (group = 0; group < community->group_count; ++group) {
87 if (community->groups[group]->pad_offset)
88 pad_cfg = community->groups[group]->pad_offset;
89 print_gpio_group(community->pcr_port_id,
90 pad_cfg, community->groups[group],
91 pad_stepping);
92 pad_cfg += community->groups[group]->pad_count * pad_stepping;
96 const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb,
97 size_t* community_count,
98 size_t* pad_stepping)
100 *pad_stepping = 8;
102 switch (sb->device_id) {
103 case PCI_DEVICE_ID_INTEL_H110:
104 case PCI_DEVICE_ID_INTEL_H170:
105 case PCI_DEVICE_ID_INTEL_Z170:
106 case PCI_DEVICE_ID_INTEL_Q170:
107 case PCI_DEVICE_ID_INTEL_Q150:
108 case PCI_DEVICE_ID_INTEL_B150:
109 case PCI_DEVICE_ID_INTEL_C236:
110 case PCI_DEVICE_ID_INTEL_C232:
111 case PCI_DEVICE_ID_INTEL_QM170:
112 case PCI_DEVICE_ID_INTEL_HM170:
113 case PCI_DEVICE_ID_INTEL_CM236:
114 case PCI_DEVICE_ID_INTEL_H270:
115 case PCI_DEVICE_ID_INTEL_Z270:
116 case PCI_DEVICE_ID_INTEL_Q270:
117 case PCI_DEVICE_ID_INTEL_Q250:
118 case PCI_DEVICE_ID_INTEL_B250:
119 case PCI_DEVICE_ID_INTEL_Z370:
120 case PCI_DEVICE_ID_INTEL_H310C:
121 case PCI_DEVICE_ID_INTEL_X299:
122 *community_count = ARRAY_SIZE(sunrise_communities);
123 return sunrise_communities;
124 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
125 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
126 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
127 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
128 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
129 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
130 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
131 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
132 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
133 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
134 *community_count = ARRAY_SIZE(sunrise_lp_communities);
135 return sunrise_lp_communities;
136 case PCI_DEVICE_ID_INTEL_C621:
137 case PCI_DEVICE_ID_INTEL_C622:
138 case PCI_DEVICE_ID_INTEL_C624:
139 case PCI_DEVICE_ID_INTEL_C625:
140 case PCI_DEVICE_ID_INTEL_C626:
141 case PCI_DEVICE_ID_INTEL_C627:
142 case PCI_DEVICE_ID_INTEL_C628:
143 case PCI_DEVICE_ID_INTEL_C629:
144 case PCI_DEVICE_ID_INTEL_C621A:
145 case PCI_DEVICE_ID_INTEL_C627A:
146 case PCI_DEVICE_ID_INTEL_C629A:
147 case PCI_DEVICE_ID_INTEL_C624_SUPER:
148 case PCI_DEVICE_ID_INTEL_C627_SUPER_1:
149 case PCI_DEVICE_ID_INTEL_C621_SUPER:
150 case PCI_DEVICE_ID_INTEL_C627_SUPER_2:
151 case PCI_DEVICE_ID_INTEL_C628_SUPER:
152 case PCI_DEVICE_ID_INTEL_C621A_SUPER:
153 case PCI_DEVICE_ID_INTEL_C627A_SUPER:
154 case PCI_DEVICE_ID_INTEL_C629A_SUPER:
155 *community_count = ARRAY_SIZE(lewisburg_communities);
156 return lewisburg_communities;
157 case PCI_DEVICE_ID_INTEL_EBG:
158 *pad_stepping = 16;
159 *community_count = ARRAY_SIZE(emmitsburg_communities);
160 return emmitsburg_communities;
161 case PCI_DEVICE_ID_INTEL_DNV_LPC:
162 *community_count = ARRAY_SIZE(denverton_communities);
163 return denverton_communities;
164 case PCI_DEVICE_ID_INTEL_APL_LPC:
165 *community_count = ARRAY_SIZE(apl_communities);
166 return apl_communities;
167 case PCI_DEVICE_ID_INTEL_GLK_LPC:
168 *community_count = ARRAY_SIZE(glk_communities);
169 *pad_stepping = 16;
170 return glk_communities;
171 case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
172 case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
173 case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
174 *community_count = ARRAY_SIZE(cannonlake_pch_lp_communities);
175 *pad_stepping = 16;
176 return cannonlake_pch_lp_communities;
177 case PCI_DEVICE_ID_INTEL_H310:
178 case PCI_DEVICE_ID_INTEL_H370:
179 case PCI_DEVICE_ID_INTEL_Z390:
180 case PCI_DEVICE_ID_INTEL_Q370:
181 case PCI_DEVICE_ID_INTEL_B360:
182 case PCI_DEVICE_ID_INTEL_C246:
183 case PCI_DEVICE_ID_INTEL_C242:
184 case PCI_DEVICE_ID_INTEL_QM370:
185 case PCI_DEVICE_ID_INTEL_HM370:
186 case PCI_DEVICE_ID_INTEL_CM246:
187 *community_count = ARRAY_SIZE(cannonlake_pch_h_communities);
188 *pad_stepping = 16;
189 return cannonlake_pch_h_communities;
190 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
191 *community_count = ARRAY_SIZE(icelake_pch_h_communities);
192 *pad_stepping = 16;
193 return icelake_pch_h_communities;
194 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
195 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
196 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
197 case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
198 case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
199 *community_count = ARRAY_SIZE(tigerlake_pch_lp_communities);
200 *pad_stepping = 16;
201 return tigerlake_pch_lp_communities;
202 case PCI_DEVICE_ID_INTEL_Q570:
203 case PCI_DEVICE_ID_INTEL_Z590:
204 case PCI_DEVICE_ID_INTEL_H570:
205 case PCI_DEVICE_ID_INTEL_B560:
206 case PCI_DEVICE_ID_INTEL_H510:
207 case PCI_DEVICE_ID_INTEL_WM590:
208 case PCI_DEVICE_ID_INTEL_QM580:
209 case PCI_DEVICE_ID_INTEL_HM570:
210 case PCI_DEVICE_ID_INTEL_C252:
211 case PCI_DEVICE_ID_INTEL_C256:
212 case PCI_DEVICE_ID_INTEL_W580:
213 *community_count = ARRAY_SIZE(tigerlake_pch_h_communities);
214 *pad_stepping = 16;
215 return tigerlake_pch_h_communities;
216 case PCI_DEVICE_ID_INTEL_H610E:
217 case PCI_DEVICE_ID_INTEL_Q670E:
218 case PCI_DEVICE_ID_INTEL_R680E:
219 case PCI_DEVICE_ID_INTEL_H610:
220 case PCI_DEVICE_ID_INTEL_B660:
221 case PCI_DEVICE_ID_INTEL_H670:
222 case PCI_DEVICE_ID_INTEL_Q670:
223 case PCI_DEVICE_ID_INTEL_Z690:
224 case PCI_DEVICE_ID_INTEL_W680:
225 case PCI_DEVICE_ID_INTEL_WM690:
226 case PCI_DEVICE_ID_INTEL_HM670:
227 case PCI_DEVICE_ID_INTEL_W790:
228 case PCI_DEVICE_ID_INTEL_Z790:
229 case PCI_DEVICE_ID_INTEL_H770:
230 case PCI_DEVICE_ID_INTEL_B760:
231 case PCI_DEVICE_ID_INTEL_HM770:
232 case PCI_DEVICE_ID_INTEL_WM790:
233 case PCI_DEVICE_ID_INTEL_C262:
234 case PCI_DEVICE_ID_INTEL_C266:
235 *community_count = ARRAY_SIZE(alderlake_pch_h_communities);
236 *pad_stepping = 16;
237 return alderlake_pch_h_communities;
238 case PCI_DEVICE_ID_INTEL_ADL_P:
239 case PCI_DEVICE_ID_INTEL_ADL_M:
240 case PCI_DEVICE_ID_INTEL_RPL_P:
241 *community_count = ARRAY_SIZE(alderlake_pch_p_communities);
242 *pad_stepping = 16;
243 return alderlake_pch_p_communities;
244 case PCI_DEVICE_ID_INTEL_JSL:
245 *community_count = ARRAY_SIZE(jasperlake_pch_communities);
246 *pad_stepping = 16;
247 return jasperlake_pch_communities;
248 case PCI_DEVICE_ID_INTEL_EHL:
249 *community_count = ARRAY_SIZE(elkhartlake_pch_communities);
250 *pad_stepping = 16;
251 return elkhartlake_pch_communities;
253 default:
254 return NULL;
258 void print_gpio_groups(struct pci_dev *const sb)
260 size_t community_count;
261 const struct gpio_community *const *communities;
262 size_t pad_stepping;
264 communities = get_gpio_communities(sb, &community_count, &pad_stepping);
266 if (!communities)
267 return;
269 pcr_init(sb);
271 printf("\n============= GPIOS =============\n\n");
273 for (; community_count; --community_count)
274 print_gpio_community(*communities++, pad_stepping);