soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION
[coreboot2.git] / util / inteltool / inteltool.h
blob07b9a72c3b8afeeafc509522dba82065e926d849
1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /* SPDX-License-Identifier: GPL-2.0-only */
4 #ifndef INTELTOOL_H
5 #define INTELTOOL_H 1
7 #if defined(__linux__)
8 #include <linux/stddef.h>
9 #endif
10 #include <arch/mmio.h>
11 #include <commonlib/helpers.h>
13 #include <stdint.h>
15 #if defined(__linux__)
16 #include <sys/io.h>
17 #endif
18 #if (defined(__MACH__) && defined(__APPLE__))
19 /* DirectHW is available here: https://www.coreboot.org/DirectHW */
20 #define __DARWIN__
21 #include <DirectHW/DirectHW.h>
22 #endif
24 #ifdef __NetBSD__
25 #include <pciutils/pci.h>
26 #else
27 #include <pci/pci.h>
28 #endif
30 /* This #include is needed for freebsd_{rd,wr}msr. */
31 #if defined(__FreeBSD__)
32 #include <machine/cpufunc.h>
33 #endif
35 #ifdef __NetBSD__
36 static inline uint8_t inb(unsigned port)
38 uint8_t data;
39 __asm volatile("inb %w1,%0" : "=a" (data) : "d" (port));
40 return data;
42 static inline uint16_t inw(unsigned port)
44 uint16_t data;
45 __asm volatile("inw %w1,%0": "=a" (data) : "d" (port));
46 return data;
48 static inline uint32_t inl(unsigned port)
50 uint32_t data;
51 __asm volatile("inl %w1,%0": "=a" (data) : "d" (port));
52 return data;
54 #endif
56 #define INTELTOOL_VERSION "1.0"
58 /* Tested chipsets: */
59 #define PCI_VENDOR_ID_INTEL 0x8086
60 #define PCI_DEVICE_ID_INTEL_ICH 0x2410
61 #define PCI_DEVICE_ID_INTEL_ICH0 0x2420
62 #define PCI_DEVICE_ID_INTEL_ICH2 0x2440
63 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
64 #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
65 #define PCI_DEVICE_ID_INTEL_ICH5 0x24d0
66 #define PCI_DEVICE_ID_INTEL_ICH6 0x2640
67 #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
68 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
69 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
70 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
71 #define PCI_DEVICE_ID_INTEL_NM10 0x27bc
72 #define PCI_DEVICE_ID_INTEL_ICH8 0x2810
73 #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
74 #define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811
75 #define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
76 #define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
77 #define PCI_DEVICE_ID_INTEL_ICH9R 0x2916
78 #define PCI_DEVICE_ID_INTEL_ICH9 0x2918
79 #define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
80 #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
81 #define PCI_DEVICE_ID_INTEL_ICH10DO 0x3a14
82 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
83 #define PCI_DEVICE_ID_INTEL_ICH10 0x3a18
84 #define PCI_DEVICE_ID_INTEL_ICH10D 0x3a1a
85 #define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00
86 #define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01
87 #define PCI_DEVICE_ID_INTEL_P55 0x3b02
88 #define PCI_DEVICE_ID_INTEL_PM55 0x3b03
89 #define PCI_DEVICE_ID_INTEL_H55 0x3b06
90 #define PCI_DEVICE_ID_INTEL_QM57 0x3b07
91 #define PCI_DEVICE_ID_INTEL_H57 0x3b08
92 #define PCI_DEVICE_ID_INTEL_HM55 0x3b09
93 #define PCI_DEVICE_ID_INTEL_Q57 0x3b0a
94 #define PCI_DEVICE_ID_INTEL_HM57 0x3b0b
95 #define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d
96 #define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e
97 #define PCI_DEVICE_ID_INTEL_QS57 0x3b0f
98 #define PCI_DEVICE_ID_INTEL_3400 0x3b12
99 #define PCI_DEVICE_ID_INTEL_3420 0x3b14
100 #define PCI_DEVICE_ID_INTEL_3450 0x3b16
101 #define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e
102 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
103 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_U 0x3482
104 #define PCI_DEVICE_ID_INTEL_Z68 0x1c44
105 #define PCI_DEVICE_ID_INTEL_P67 0x1c46
106 #define PCI_DEVICE_ID_INTEL_UM67 0x1c47
107 #define PCI_DEVICE_ID_INTEL_HM65 0x1c49
108 #define PCI_DEVICE_ID_INTEL_H67 0x1c4a
109 #define PCI_DEVICE_ID_INTEL_HM67 0x1c4b
110 #define PCI_DEVICE_ID_INTEL_Q65 0x1c4c
111 #define PCI_DEVICE_ID_INTEL_QS67 0x1c4d
112 #define PCI_DEVICE_ID_INTEL_Q67 0x1c4e
113 #define PCI_DEVICE_ID_INTEL_QM67 0x1c4f
114 #define PCI_DEVICE_ID_INTEL_B65 0x1c50
115 #define PCI_DEVICE_ID_INTEL_C202 0x1c52
116 #define PCI_DEVICE_ID_INTEL_C204 0x1c54
117 #define PCI_DEVICE_ID_INTEL_C206 0x1c56
118 #define PCI_DEVICE_ID_INTEL_H61 0x1c5c
119 #define PCI_DEVICE_ID_INTEL_Z77 0x1e44
120 #define PCI_DEVICE_ID_INTEL_Z75 0x1e46
121 #define PCI_DEVICE_ID_INTEL_Q77 0x1e47
122 #define PCI_DEVICE_ID_INTEL_Q75 0x1e48
123 #define PCI_DEVICE_ID_INTEL_B75 0x1e49
124 #define PCI_DEVICE_ID_INTEL_H77 0x1e4a
125 #define PCI_DEVICE_ID_INTEL_C216 0x1e53
126 #define PCI_DEVICE_ID_INTEL_QM77 0x1e55
127 #define PCI_DEVICE_ID_INTEL_QS77 0x1e56
128 #define PCI_DEVICE_ID_INTEL_HM77 0x1e57
129 #define PCI_DEVICE_ID_INTEL_UM77 0x1e58
130 #define PCI_DEVICE_ID_INTEL_HM76 0x1e59
131 #define PCI_DEVICE_ID_INTEL_HM75 0x1e5d
132 #define PCI_DEVICE_ID_INTEL_HM70 0x1e5e
133 #define PCI_DEVICE_ID_INTEL_NM70 0x1e5f
134 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
135 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
136 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
137 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3
138 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
139 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102
140 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120
141 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141
142 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03
143 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41
144 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL 0x9d43
145 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL 0x9d46
146 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL 0x9d48
147 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL 0x9d53
148 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL 0x9d56
149 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL 0x9d58
150 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50
151 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e
152 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b
153 #define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84
154 #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284
155 #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285
156 #define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER 0xa081
157 #define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM 0xa082
158 #define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE 0xa083
159 #define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER 0xa086
160 #define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM 0xa087
161 #define PCI_DEVICE_ID_INTEL_H110 0xa143
162 #define PCI_DEVICE_ID_INTEL_H170 0xa144
163 #define PCI_DEVICE_ID_INTEL_Z170 0xa145
164 #define PCI_DEVICE_ID_INTEL_Q170 0xa146
165 #define PCI_DEVICE_ID_INTEL_Q150 0xa147
166 #define PCI_DEVICE_ID_INTEL_B150 0xa148
167 #define PCI_DEVICE_ID_INTEL_C236 0xa149
168 #define PCI_DEVICE_ID_INTEL_C232 0xa14a
169 #define PCI_DEVICE_ID_INTEL_QM170 0xa14d
170 #define PCI_DEVICE_ID_INTEL_HM170 0xa14e
171 #define PCI_DEVICE_ID_INTEL_CM236 0xa150
172 #define PCI_DEVICE_ID_INTEL_HM175 0xa152
173 #define PCI_DEVICE_ID_INTEL_QM175 0xa153
174 #define PCI_DEVICE_ID_INTEL_CM238 0xa154
176 #define PCI_DEVICE_ID_INTEL_C621 0xa1c1
177 #define PCI_DEVICE_ID_INTEL_C622 0xa1c2
178 #define PCI_DEVICE_ID_INTEL_C624 0xa1c3
179 #define PCI_DEVICE_ID_INTEL_C625 0xa1c4
180 #define PCI_DEVICE_ID_INTEL_C626 0xa1c5
181 #define PCI_DEVICE_ID_INTEL_C627 0xa1c6
182 #define PCI_DEVICE_ID_INTEL_C628 0xa1c7
183 #define PCI_DEVICE_ID_INTEL_C629 0xa1ca
184 #define PCI_DEVICE_ID_INTEL_C621A 0xa1cb
185 #define PCI_DEVICE_ID_INTEL_C627A 0xa1cc
186 #define PCI_DEVICE_ID_INTEL_C629A 0xa1cd
187 #define PCI_DEVICE_ID_INTEL_C624_SUPER 0xa242
188 #define PCI_DEVICE_ID_INTEL_C627_SUPER_1 0xa243
189 #define PCI_DEVICE_ID_INTEL_C621_SUPER 0xa244
190 #define PCI_DEVICE_ID_INTEL_C627_SUPER_2 0xa245
191 #define PCI_DEVICE_ID_INTEL_C628_SUPER 0xa246
192 #define PCI_DEVICE_ID_INTEL_C621A_SUPER 0xa24a
193 #define PCI_DEVICE_ID_INTEL_C627A_SUPER 0xa24b
194 #define PCI_DEVICE_ID_INTEL_C629A_SUPER 0xa24c
196 #define PCI_DEVICE_ID_INTEL_EBG 0x1b81
198 #define PCI_DEVICE_ID_INTEL_H270 0xa2c4
199 #define PCI_DEVICE_ID_INTEL_Z270 0xa2c5
200 #define PCI_DEVICE_ID_INTEL_Q270 0xa2c6
201 #define PCI_DEVICE_ID_INTEL_Q250 0xa2c7
202 #define PCI_DEVICE_ID_INTEL_B250 0xa2c8
203 #define PCI_DEVICE_ID_INTEL_Z370 0xa2c9
204 #define PCI_DEVICE_ID_INTEL_H310C 0xa2ca
205 #define PCI_DEVICE_ID_INTEL_X299 0xa2d2
207 #define PCI_DEVICE_ID_INTEL_H310 0xa303
208 #define PCI_DEVICE_ID_INTEL_H370 0xa304
209 #define PCI_DEVICE_ID_INTEL_Z390 0xa305
210 #define PCI_DEVICE_ID_INTEL_Q370 0xa306
211 #define PCI_DEVICE_ID_INTEL_B360 0xa308
212 #define PCI_DEVICE_ID_INTEL_C246 0xa309
213 #define PCI_DEVICE_ID_INTEL_C242 0xa30a
214 #define PCI_DEVICE_ID_INTEL_QM370 0xa30c
215 #define PCI_DEVICE_ID_INTEL_HM370 0xa30d
216 #define PCI_DEVICE_ID_INTEL_CM246 0xa30e
218 #define PCI_DEVICE_ID_INTEL_Q570 0x4384
219 #define PCI_DEVICE_ID_INTEL_Z590 0x4385
220 #define PCI_DEVICE_ID_INTEL_H570 0x4386
221 #define PCI_DEVICE_ID_INTEL_B560 0x4387
222 #define PCI_DEVICE_ID_INTEL_H510 0x4388
223 #define PCI_DEVICE_ID_INTEL_WM590 0x4389
224 #define PCI_DEVICE_ID_INTEL_QM580 0x438a
225 #define PCI_DEVICE_ID_INTEL_HM570 0x438b
226 #define PCI_DEVICE_ID_INTEL_C252 0x438c
227 #define PCI_DEVICE_ID_INTEL_C256 0x438d
228 #define PCI_DEVICE_ID_INTEL_W580 0x438f
230 #define PCI_DEVICE_ID_INTEL_H610 0x7a87
231 #define PCI_DEVICE_ID_INTEL_B660 0x7a86
232 #define PCI_DEVICE_ID_INTEL_H670 0x7a85
233 #define PCI_DEVICE_ID_INTEL_Q670 0x7a83
234 #define PCI_DEVICE_ID_INTEL_Z690 0x7a84
235 #define PCI_DEVICE_ID_INTEL_W680 0x7a88
236 #define PCI_DEVICE_ID_INTEL_WM690 0x7a8d
237 #define PCI_DEVICE_ID_INTEL_HM670 0x7a8c
238 #define PCI_DEVICE_ID_INTEL_R680E 0x7a90
239 #define PCI_DEVICE_ID_INTEL_Q670E 0x7a91
240 #define PCI_DEVICE_ID_INTEL_H610E 0x7a92
242 #define PCI_DEVICE_ID_INTEL_W790 0x7a8a
243 #define PCI_DEVICE_ID_INTEL_Z790 0x7a04
244 #define PCI_DEVICE_ID_INTEL_H770 0x7a05
245 #define PCI_DEVICE_ID_INTEL_B760 0x7a06
246 #define PCI_DEVICE_ID_INTEL_HM770 0x7a0c
247 #define PCI_DEVICE_ID_INTEL_WM790 0x7a0d
248 #define PCI_DEVICE_ID_INTEL_C262 0x7a14
249 #define PCI_DEVICE_ID_INTEL_C266 0x7a13
251 #define PCI_DEVICE_ID_INTEL_82810 0x7120
252 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
253 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
254 #define PCI_DEVICE_ID_INTEL_82830M 0x3575
255 #define PCI_DEVICE_ID_INTEL_82845 0x1a30
256 #define PCI_DEVICE_ID_INTEL_82865 0x2570
257 #define PCI_DEVICE_ID_INTEL_82915 0x2580
258 #define PCI_DEVICE_ID_INTEL_82945P 0x2770
259 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
260 #define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
261 #define PCI_DEVICE_ID_INTEL_82946 0x2970
262 #define PCI_DEVICE_ID_INTEL_82965PM 0x2a00
263 #define PCI_DEVICE_ID_INTEL_82Q965 0x2990
264 #define PCI_DEVICE_ID_INTEL_82975X 0x277c
265 #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
266 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0
267 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
268 #define PCI_DEVICE_ID_INTEL_82X38 0x29e0
269 #define PCI_DEVICE_ID_INTEL_32X0 0x29f0
270 #define PCI_DEVICE_ID_INTEL_82XX4X 0x2a40
271 #define PCI_DEVICE_ID_INTEL_82Q45 0x2e10
272 #define PCI_DEVICE_ID_INTEL_82G45 0x2e20
273 #define PCI_DEVICE_ID_INTEL_82G41 0x2e30
274 #define PCI_DEVICE_ID_INTEL_82B43 0x2e40
275 #define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90
277 #define PCI_DEVICE_ID_INTEL_C8_MOBILE 0x8c41
278 #define PCI_DEVICE_ID_INTEL_C8_DESKTOP 0x8c42
279 #define PCI_DEVICE_ID_INTEL_Z87 0x8c44
280 #define PCI_DEVICE_ID_INTEL_Z85 0x8c46
281 #define PCI_DEVICE_ID_INTEL_HM86 0x8c49
282 #define PCI_DEVICE_ID_INTEL_H87 0x8c4a
283 #define PCI_DEVICE_ID_INTEL_HM87 0x8c4b
284 #define PCI_DEVICE_ID_INTEL_Q85 0x8c4c
285 #define PCI_DEVICE_ID_INTEL_Q87 0x8c4e
286 #define PCI_DEVICE_ID_INTEL_QM87 0x8c4f
287 #define PCI_DEVICE_ID_INTEL_B85 0x8c50
288 #define PCI_DEVICE_ID_INTEL_C222 0x8c52
289 #define PCI_DEVICE_ID_INTEL_C224 0x8c54
290 #define PCI_DEVICE_ID_INTEL_C226 0x8c56
291 #define PCI_DEVICE_ID_INTEL_H81 0x8c5c
293 #define PCI_DEVICE_ID_INTEL_C9_MOBILE 0x8cc1
294 #define PCI_DEVICE_ID_INTEL_C9_DESKTOP 0x8cc2
295 #define PCI_DEVICE_ID_INTEL_HM97 0x8cc3
296 #define PCI_DEVICE_ID_INTEL_Z97 0x8cc4
297 #define PCI_DEVICE_ID_INTEL_H97 0x8cc6
299 #define PCI_DEVICE_ID_INTEL_82X58 0x3405
300 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
301 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
302 #define PCI_DEVICE_ID_INTEL_I63XX 0x2670
304 #define PCI_DEVICE_ID_INTEL_I5000X 0x25c0
305 #define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0
306 #define PCI_DEVICE_ID_INTEL_I5000V 0x25d4
307 #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8
309 #define PCI_DEVICE_ID_INTEL_ADL_P 0x5182
310 #define PCI_DEVICE_ID_INTEL_ADL_M 0x5187
311 #define PCI_DEVICE_ID_INTEL_RPL_P 0x519d
313 #define PCI_DEVICE_ID_INTEL_EHL 0x4b00
314 #define PCI_DEVICE_ID_INTEL_JSL 0x4d87
316 /* untested, but almost identical to D-series */
317 #define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
319 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180
320 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
321 #define PCI_DEVICE_ID_INTEL_82443BX 0x7190
322 #define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
324 /* 82371AB/EB/MB use the same device ID value. */
325 #define PCI_DEVICE_ID_INTEL_82371XX 0x7110
327 /* Bay Trail */
328 #define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */
329 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c
330 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31
331 #define CPUID_BAYTRAIL 0x30670
333 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
334 #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc
335 #define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31E8
337 /* Intel starts counting these generations with the integration of the DRAM controller */
338 #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
339 #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
340 #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */
341 #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */
342 #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */
343 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x0150 /* Ivy Bridge (Desktop) */
344 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M 0x0154 /* Ivy Bridge (Mobile) */
345 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */
346 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */
347 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */
348 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */
349 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */
350 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
351 #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
352 #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D 0x1610 /* Broadwell (Desktop) */
353 #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M 0x1614 /* Broadwell (Mobile) */
354 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */
355 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */
356 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */
357 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */
358 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */
359 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */
360 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E 0x2020 /* Skylake-E (Server) */
361 #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */
362 #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */
363 #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */
364 #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */
365 #define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1 0x3ed0 /* Coffeelake (Mobile) */
366 #define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2 0x3e34 /* Whiskeylake (Mobile) */
367 #define PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U 0x8a12 /* Icelake U */
368 #define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */
369 #define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */
370 #define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */
371 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */
372 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */
373 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */
374 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4 0x9a12 /* Tigerlake UP4 4 Cores */
375 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4 0x9a16 /* Tigerlake H 4 Cores */
376 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6 0x9a26 /* Tigerlake H 6 Cores */
377 #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8 0x9a36 /* Tigerlake H 8 Cores */
378 #define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */
379 #define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */
380 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_8 0x4660 /* Alderlake S LGA 8+8 */
381 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_4 0x4668 /* Alderlake S LGA 8+4 */
382 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_4 0x4648 /* Alderlake S LGA 6+4 */
383 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_0 0x4670 /* Alderlake S LGA 8+0 */
384 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_0 0x4650 /* Alderlake S LGA 6+0 */
385 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_8_8 0x4637 /* Alderlake HX 8+8 */
386 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_6_8 0x463B /* Alderlake HX 6+8 */
387 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_4_8 0x4623 /* Alderlake HX 4+8 */
388 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8 0x4641 /* Alderlake P 6+8 */
389 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8 0x4621 /* Alderlake P 4+8 */
390 #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8 0x4601 /* Alderlake P 2+8 */
391 #define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6 0xa706 /* Raptorlake H 8+6 */
393 /* Intel GPUs */
394 #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982
395 #define PCI_DEVICE_ID_INTEL_G35_EXPRESS_1 0x2983
396 #define PCI_DEVICE_ID_INTEL_965_EXPRESS 0x2a02
397 #define PCI_DEVICE_ID_INTEL_965_EXPRESS_1 0x2a03
398 #define PCI_DEVICE_ID_INTEL_965_EXPRESS_2 0x2a12
399 #define PCI_DEVICE_ID_INTEL_965_EXPRESS_3 0x2a13
400 #define PCI_DEVICE_ID_INTEL_4_SERIES 0x2a42
401 #define PCI_DEVICE_ID_INTEL_4_SERIES_1 0x2a43
402 #define PCI_DEVICE_ID_INTEL_G45 0x2e22
403 #define PCI_DEVICE_ID_INTEL_G45_1 0x2e23
404 #define PCI_DEVICE_ID_INTEL_Q45 0x2e12
405 #define PCI_DEVICE_ID_INTEL_Q45_1 0x2e13
406 #define PCI_DEVICE_ID_INTEL_G41 0x2e32
407 #define PCI_DEVICE_ID_INTEL_G41_1 0x2e33
408 #define PCI_DEVICE_ID_INTEL_B43 0x2e42
409 #define PCI_DEVICE_ID_INTEL_B43_1 0x2e43
410 #define PCI_DEVICE_ID_INTEL_B43_2 0x2e92
411 #define PCI_DEVICE_ID_INTEL_B43_3 0x2e93
412 #define PCI_DEVICE_ID_INTEL_HD_GRAPHICS 0x0046
413 #define PCI_DEVICE_ID_INTEL_HD_GRAPHICS_1 0x0042
414 #define PCI_DEVICE_ID_INTEL_HD_GRAPHICS_2 0x0106
415 #define PCI_DEVICE_ID_INTEL_HD_2000 0x0102
416 #define PCI_DEVICE_ID_INTEL_HD_2000_1 0x0106
417 #define PCI_DEVICE_ID_INTEL_HD_3000 0x0116
418 #define PCI_DEVICE_ID_INTEL_HD_3000_1 0x0112
419 #define PCI_DEVICE_ID_INTEL_HD_3000_2 0x0116
420 #define PCI_DEVICE_ID_INTEL_HD_3000_3 0x0122
421 #define PCI_DEVICE_ID_INTEL_HD_3000_4 0x0126
422 #define PCI_DEVICE_ID_INTEL_HD_3000_5 0x0116
423 #define PCI_DEVICE_ID_INTEL_HD_2500 0x0152
424 #define PCI_DEVICE_ID_INTEL_HD_2500_1 0x0156
425 #define PCI_DEVICE_ID_INTEL_HD_2500_2 0x015A
426 #define PCI_DEVICE_ID_INTEL_HD_4000 0x0162
427 #define PCI_DEVICE_ID_INTEL_HD_4000_1 0x0166
428 #define PCI_DEVICE_ID_INTEL_HD_4000_2 0x016A
429 #define PCI_DEVICE_ID_INTEL_HD_4600 0x0412
430 #define PCI_DEVICE_ID_INTEL_HD_4600_1 0x0416
431 #define PCI_DEVICE_ID_INTEL_HD_4400 0x041E
432 #define PCI_DEVICE_ID_INTEL_HD_4400_1 0x0A16
433 #define PCI_DEVICE_ID_INTEL_HD_5000 0x0422
434 #define PCI_DEVICE_ID_INTEL_HD_5000_1 0x0426
435 #define PCI_DEVICE_ID_INTEL_HD_5000_2 0x042A
436 #define PCI_DEVICE_ID_INTEL_HD_510 0x1902
437 #define PCI_DEVICE_ID_INTEL_HD_515 0x191E
438 #define PCI_DEVICE_ID_INTEL_HD_520 0x1916
439 #define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B
440 #define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912
441 #define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C
442 #define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E
443 #define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0
444 #define PCI_DEVICE_ID_INTEL_UHD_620_1 0x5917
445 #define PCI_DEVICE_ID_INTEL_UHD_620_2 0x3EA0
446 #define PCI_DEVICE_ID_INTEL_UHD_620_3 0x5916
447 #define PCI_DEVICE_ID_INTEL_UHD_630_1 0x3E92
448 #define PCI_DEVICE_ID_INTEL_UHD_630_2 0x3E9B
449 #define PCI_DEVICE_ID_INTEL_UHD_630_3 0x3E91
450 #define PCI_DEVICE_ID_INTEL_UHD_630_4 0x5912
451 #define PCI_DEVICE_ID_INTEL_UHD_630_5 0x591B
452 #define PCI_DEVICE_ID_INTEL_UHD_630_6 0x5902
453 #define PCI_DEVICE_ID_INTEL_UHD_630_7 0x3E98
454 #define PCI_DEVICE_ID_INTEL_UHD_640 0x5926
455 #define PCI_DEVICE_ID_INTEL_IRIS_540 0x1926
456 #define PCI_DEVICE_ID_INTEL_IRIS_550 0x1927
457 #define PCI_DEVICE_ID_INTEL_IRIS_PRO_580 0x193B
458 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_650 0x5927
459 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5
460 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52
461 #define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41
462 #define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40
463 #define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49
464 #define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60
465 #define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68
466 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78
467 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70
468 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
469 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_2 0x4682
470 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_3 0x4690
471 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_4 0x4692
472 #define PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE 0xa7a0
474 #if !defined(__DARWIN__) && !defined(__FreeBSD__)
475 typedef struct { uint32_t hi, lo; } msr_t;
476 #endif
477 #if defined (__FreeBSD__)
478 /* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */
479 #undef rdmsr
480 #undef wrmsr
481 #define rdmsr freebsd_rdmsr
482 #define wrmsr freebsd_wrmsr
483 typedef struct { uint32_t hi, lo; } msr_t;
484 #endif
485 typedef struct { uint16_t addr; int size; char *name; } io_register_t;
486 typedef struct {
487 uint32_t eax;
488 uint32_t ebx;
489 uint32_t ecx;
490 uint32_t edx;
491 } cpuid_result_t;
493 void *map_physical(uint64_t phys_addr, size_t len);
494 void unmap_physical(void *virt_addr, size_t len);
496 unsigned int cpuid(unsigned int op);
497 int print_intel_msrs(unsigned int range_start, unsigned int range_end);
498 int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file);
499 int print_pmbase(struct pci_dev *sb, struct pci_access *pacc);
500 int print_lpc(struct pci_dev *sb, struct pci_access *pacc);
501 int print_rcba(struct pci_dev *sb);
502 void print_iobp(struct pci_dev *sb, volatile uint8_t *rcba);
503 int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
504 const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb,
505 size_t* community_count,
506 size_t* pad_stepping);
507 void print_gpio_groups(struct pci_dev *sb);
508 int print_epbar(struct pci_dev *nb);
509 int print_dmibar(struct pci_dev *nb);
510 int print_pciexbar(struct pci_dev *nb);
511 int print_ambs(struct pci_dev *nb, struct pci_access *pacc);
512 int print_spi(struct pci_dev *sb);
513 int print_gfx(struct pci_dev *gfx);
514 int print_ahci(struct pci_dev *ahci);
515 int print_sgx(void);
516 void print_tme(void);
517 void print_keylocker(void);
518 void ivybridge_dump_timings(const char *dump_spd_file);
520 #endif