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soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION
[coreboot2.git] / util / inteltool / pcie.c
blobfb29d3201ec2043d8c82bb7ca90af20131ccd62b
1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /* SPDX-License-Identifier: GPL-2.0-only */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6 #include <inttypes.h>
7 #include "inteltool.h"
8
9 /* 320766 */
10 static const io_register_t nehalem_dmi_registers[] = {
11 { 0x00, 4, "DMIVCH" }, // DMI Virtual Channel Capability Header
12 { 0x04, 4, "DMIVCCAP1" }, // DMI Port VC Capability Register 1
13 { 0x08, 4, "DMIVCCAP2" }, // DMI Port VC Capability Register 2
14 { 0x0C, 4, "DMIVCCTL" }, // DMI Port VC Control
15 { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
16 { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
17 /* { 0x18, 2, "RSVD" }, // Reserved */
18 { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
19 { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
20 { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
21 /* { 0x24, 2, "RSVD" }, // Reserved */
22 { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
23 /* ... - Reserved */
24 { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities
25 { 0x88, 2, "DMILCTL" }, // DMI Link Control
26 { 0x8A, 2, "DMILSTS" }, // DMI Link Status
27 /* ... - Reserved */
28 };
29
30 /* 322812 */
31 static const io_register_t westmere_dmi_registers[] = {
32 { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
33 { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
34 { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
35 { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control
36 /* { 0x0E, 2, "RSVD" }, // Reserved */
37 { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
38 { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
39 /* { 0x18, 2, "RSVD" }, // Reserved */
40 { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
41 { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
42 { 0x20, 4, "DMIVC1RCTL1" }, // DMI VC1 Resource Control
43 /* { 0x24, 2, "RSVD" }, // Reserved */
44 { 0x26, 2, "DMIC1RSTS" }, // DMI VC1 Resource Status
45 /* ... - Reserved */
46 { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities
47 { 0x88, 2, "DMILCTL" }, // DMI Link Control
48 { 0x8A, 2, "DMILSTS" }, // DMI Link Status
49 /* ... - Reserved */
50 };
51
52 static const io_register_t sandybridge_dmi_registers[] = {
53 { 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability
54 { 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1
55 { 0x08, 4, "DMI PVVAP2" }, // DMI Port VC Capability Register 2
56 { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
57 /* { 0x0E, 2, "RSVD" }, // Reserved */
58 { 0x10, 4, "DMI VC0RCAP" }, // DMI VC0 Resource Capability
59 { 0x14, 4, "DMI VC0RCTL" }, // DMI VC0 Resource Control
60 /* { 0x18, 2, "RSVD" }, // Reserved */
61 { 0x1A, 2, "DMI VC0RSTS" }, // DMI VC0 Resource Status
62 { 0x1C, 4, "DMI VC1RCAP" }, // DMI VC1 Resource Capability
63 { 0x20, 4, "DMI VC1RCTL" }, // DMI VC1 Resource Control
64 /* { 0x24, 2, "RSVD" }, // Reserved */
65 { 0x26, 2, "DMI VC1RSTS" }, // DMI VC1 Resource Status
66 { 0x28, 4, "DMI VCPRCAP" }, // DMI VCp Resource Capability
67 { 0x2C, 4, "DMI VCPRCTL" }, // DMI VCp Resource Control
68 /* { 0x30, 2, "RSVD" }, // Reserved */
69 { 0x32, 2, "DMI VCPRSTS" }, // DMI VCp Resource Status
70 { 0x34, 4, "DMI VCMRCAP" }, // DMI VCm Resource Capability
71 { 0x38, 4, "DMI VCMRCTL" }, // DMI VCm Resource Control
72 /* { 0x3C, 2, "RSVD" }, // Reserved */
73 { 0x3E, 2, "DMI VCMRSTS" }, // DMI VCm Resource Status
74 /* { 0x40, 4, "RSVD" }, // Reserved */
75 { 0x44, 4, "DMI ESC" }, // DMI Element Self Description
76 /* { 0x48, 8, "RSVD" }, // Reserved */
77 { 0x50, 4, "DMI LE1D" }, // DMI Link Entry 1 Description
78 /* { 0x54, 4, "RSVD" }, // Reserved */
79 { 0x58, 4, "DMI LE1A" }, // DMI Link Entry 1 Address
80 { 0x5C, 4, "DMI LUE1A" }, // DMI Link Upper Entry 1 Address
81 { 0x60, 4, "DMI LE2D" }, // DMI Link Entry 2 Description
82 /* { 0x64, 4, "RSVD" }, // Reserved */
83 { 0x68, 4, "DMI LE2A" }, // DMI Link Entry 2 Address
84 /* { 0x6C, 4, "RSVD" }, // Reserved
85 { 0x70, 8, "RSVD" }, // Reserved
86 { 0x78, 8, "RSVD" }, // Reserved
87 { 0x80, 4, "RSVD" }, // Reserved */
88 { 0x84, 4, "LCAP" }, // Link Capabilities
89 { 0x88, 2, "LCTL" }, // Link Control
90 { 0x8A, 2, "LSTS" }, // Link Status
91 /* { 0x8C, 4, "RSVD" }, // Reserved
92 { 0x90, 4, "RSVD" }, // Reserved
93 { 0x94, 4, "RSVD" }, // Reserved */
94 { 0x98, 2, "LCTL2" }, // Link Control 2
95 { 0x9A, 2, "LSTS2" }, // Link Status 2
96 /* ... - Reserved */
97 { 0xBC0, 4, "AFE_BMUF0" }, // AFE BMU Configuration Function 0
98 { 0xBC4, 4, "RSVD" }, // Reserved
99 { 0xBC8, 4, "RSVD" }, // Reserved
100 { 0xBCC, 4, "AFE_BMUT0" }, // AFE BMU Configuration Test 0
101 /* ... - Reserved */
102 };
103
104 /*
105 * All Haswell DMI Registers per
106 *
107 * Mobile 4th Generation Intel Core TM Processor Family, Mobile Intel Pentium Processor Family,
108 * and Mobile Intel Celeron Processor Family
109 * Datasheet Volume 2
110 * 329002-002
111 */
112 static const io_register_t haswell_ult_dmi_registers[] = {
113 { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
114 { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
115 { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
116 { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
117 /* { 0x0E, 2, "RSVD" }, // Reserved */
118 { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
119 { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
120 /* { 0x18, 2, "RSVD" }, // Reserved */
121 { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
122 { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
123 { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
124 /* { 0x24, 2, "RSVD" }, // Reserved */
125 { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
126 { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability
127 { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control
128 /* { 0x30, 2, "RSVD" }, // Reserved */
129 { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status
130 { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
131 { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
132 /* { 0x3C, 2, "RSVD" }, // Reserved */
133 { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
134 { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */
135 { 0x44, 4, "DMIESD" }, // DMI Element Self Description
136 /* { 0x48, 4, "RSVD" }, // Reserved */
137 /* { 0x4C, 4, "RSVD" }, // Reserved */
138 { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
139 /* { 0x54, 4, "RSVD" }, // Reserved */
140 { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
141 { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
142 { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
143 /* { 0x64, 4, "RSVD" }, // Reserved */
144 { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
145 /* { 0x6C, 4, "RSVD" }, // Reserved */
146 /* { 0x70, 4, "RSVD" }, // Reserved */
147 /* { 0x74, 4, "RSVD" }, // Reserved */
148 /* { 0x78, 4, "RSVD" }, // Reserved */
149 /* { 0x7C, 4, "RSVD" }, // Reserved */
150 /* { 0x80, 4, "RSVD" }, // Reserved */
151 /* { 0x84, 4, "RSVD" }, // Reserved */
152 { 0x88, 2, "LCTL" }, // Link Control
153 /* ... - Reserved */
154 { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status
155 { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask
156 { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status
157 { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
158 /* ... - Reserved */
159 };
160
161 /*
162 * All Skylake-S/H DMI Registers per
163 *
164 * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2
165 * Page 117
166 * 332688-003E
167 *
168 * 6th Generation Intel Processor Families for H-Platform Volume 2 of 2
169 * Page 117
170 * 332987-002EN
171 */
172 static const io_register_t skylake_dmi_registers[] = {
173 { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
174 { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
175 { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
176 { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control
177 { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
178 { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
179 { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
180 { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
181 { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
182 { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
183 { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
184 { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
185 { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
186 { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */
187 { 0x44, 4, "DMIESD" }, // DMI Element Self Description
188 { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
189 { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
190 { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
191 { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
192 { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
193 { 0x84, 4, "LCAP" }, // Link Capabilities
194 { 0x88, 2, "LCTL" }, // Link Control
195 { 0x8A, 2, "LSTS" }, // DMI Link Status
196 { 0x98, 2, "LCTL2" }, // Link Control 2
197 { 0x9A, 2, "LSTS2" }, // DMI Link Status 2
198 { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status
199 { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask
200 { 0x1CC, 4, "DMIUESEV" }, // DMI Uncorrectable Error Mask
201 { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status
202 { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
203 };
204
205
206 /*
207 * Egress Port Root Complex MMIO configuration space
208 */
209 int print_epbar(struct pci_dev *nb)
210 {
211 int i, size = (4 * 1024);
212 volatile uint8_t *epbar;
213 uint64_t epbar_phys;
214
215 printf("\n============= EPBAR =============\n\n");
216
217 switch (nb->device_id) {
218 case PCI_DEVICE_ID_INTEL_82915:
219 case PCI_DEVICE_ID_INTEL_82945GM:
220 case PCI_DEVICE_ID_INTEL_82945GSE:
221 case PCI_DEVICE_ID_INTEL_82945P:
222 case PCI_DEVICE_ID_INTEL_82946:
223 case PCI_DEVICE_ID_INTEL_82975X:
224 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
225 break;
226 case PCI_DEVICE_ID_INTEL_82965PM:
227 case PCI_DEVICE_ID_INTEL_82Q965:
228 case PCI_DEVICE_ID_INTEL_82Q35:
229 case PCI_DEVICE_ID_INTEL_82G33:
230 case PCI_DEVICE_ID_INTEL_82Q33:
231 case PCI_DEVICE_ID_INTEL_82X38:
232 case PCI_DEVICE_ID_INTEL_32X0:
233 case PCI_DEVICE_ID_INTEL_82XX4X:
234 case PCI_DEVICE_ID_INTEL_82Q45:
235 case PCI_DEVICE_ID_INTEL_82G45:
236 case PCI_DEVICE_ID_INTEL_82G41:
237 case PCI_DEVICE_ID_INTEL_82B43:
238 case PCI_DEVICE_ID_INTEL_82B43_2:
239 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
240 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
241 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
242 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
243 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
244 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
245 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
246 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
247 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
248 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
249 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
250 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
251 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
252 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
253 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D:
254 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M:
255 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2:
256 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U:
257 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y:
258 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
259 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
260 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
261 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E:
262 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
263 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
264 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
265 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3:
266 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1:
267 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2:
268 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
269 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
270 break;
271 case PCI_DEVICE_ID_INTEL_82810:
272 case PCI_DEVICE_ID_INTEL_82810_DC:
273 case PCI_DEVICE_ID_INTEL_82810E_DC:
274 case PCI_DEVICE_ID_INTEL_82830M:
275 case PCI_DEVICE_ID_INTEL_82865:
276 printf("This northbridge does not have EPBAR.\n");
277 return 1;
278 default:
279 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
280 return 1;
281 }
282
283 epbar = map_physical(epbar_phys, size);
284
285 if (epbar == NULL) {
286 perror("Error mapping EPBAR");
287 exit(1);
288 }
289
290 printf("EPBAR = 0x%08" PRIx64 " (MEM)\n\n", epbar_phys);
291 for (i = 0; i < size; i += 4) {
292 if (read32(epbar + i))
293 printf("0x%04x: 0x%08x\n", i, read32(epbar+i));
294 }
295
296 unmap_physical((void *)epbar, size);
297 return 0;
298 }
299
300 /*
301 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
302 */
303 int print_dmibar(struct pci_dev *nb)
304 {
305 int i, size = (4 * 1024);
306 volatile uint8_t *dmibar;
307 uint64_t dmibar_phys;
308 const io_register_t *dmi_registers = NULL;
309
310 printf("\n============= DMIBAR ============\n\n");
311
312 switch (nb->device_id) {
313 case PCI_DEVICE_ID_INTEL_82915:
314 case PCI_DEVICE_ID_INTEL_82945GM:
315 case PCI_DEVICE_ID_INTEL_82945GSE:
316 case PCI_DEVICE_ID_INTEL_82945P:
317 case PCI_DEVICE_ID_INTEL_82975X:
318 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
319 break;
320 case PCI_DEVICE_ID_INTEL_82946:
321 case PCI_DEVICE_ID_INTEL_82965PM:
322 case PCI_DEVICE_ID_INTEL_82Q965:
323 case PCI_DEVICE_ID_INTEL_82Q35:
324 case PCI_DEVICE_ID_INTEL_82G33:
325 case PCI_DEVICE_ID_INTEL_82Q33:
326 case PCI_DEVICE_ID_INTEL_82X38:
327 case PCI_DEVICE_ID_INTEL_32X0:
328 case PCI_DEVICE_ID_INTEL_82XX4X:
329 case PCI_DEVICE_ID_INTEL_82Q45:
330 case PCI_DEVICE_ID_INTEL_82G45:
331 case PCI_DEVICE_ID_INTEL_82G41:
332 case PCI_DEVICE_ID_INTEL_82B43:
333 case PCI_DEVICE_ID_INTEL_82B43_2:
334 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
335 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
336 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
337 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
338 break;
339 case PCI_DEVICE_ID_INTEL_82810:
340 case PCI_DEVICE_ID_INTEL_82810_DC:
341 case PCI_DEVICE_ID_INTEL_82810E_DC:
342 case PCI_DEVICE_ID_INTEL_82865:
343 printf("This northbridge does not have DMIBAR.\n");
344 return 1;
345 case PCI_DEVICE_ID_INTEL_82X58:
346 dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
347 break;
348 case PCI_DEVICE_ID_INTEL_CORE_0TH_GEN:
349 /* DMIBAR is called DMIRCBAR in Nehalem */
350 dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; /* 31:12 */
351 dmi_registers = nehalem_dmi_registers;
352 size = ARRAY_SIZE(nehalem_dmi_registers);
353 break;
354 case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
355 dmibar_phys = pci_read_long(nb, 0x68);
356 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
357 dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */
358 dmi_registers = westmere_dmi_registers;
359 size = ARRAY_SIZE(westmere_dmi_registers);
360 break;
361 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
362 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
363 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
364 dmi_registers = sandybridge_dmi_registers;
365 size = ARRAY_SIZE(sandybridge_dmi_registers);
366 /* fall through */
367 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: /* pretty printing not implemented yet */
368 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
369 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
370 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
371 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
372 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
373 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
374 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D:
375 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M:
376 dmibar_phys = pci_read_long(nb, 0x68);
377 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
378 dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
379 break;
380 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
381 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
382 dmi_registers = haswell_ult_dmi_registers;
383 size = ARRAY_SIZE(haswell_ult_dmi_registers);
384 dmibar_phys = pci_read_long(nb, 0x68);
385 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
386 dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
387 break;
388 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2:
389 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U:
390 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y:
391 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
392 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
393 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
394 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E:
395 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
396 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
397 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
398 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3:
399 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1:
400 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2:
401 dmi_registers = skylake_dmi_registers;
402 size = ARRAY_SIZE(skylake_dmi_registers);
403 dmibar_phys = pci_read_long(nb, 0x68);
404 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
405 dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
406 break;
407 default:
408 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
409 return 1;
410 }
411
412 dmibar = map_physical(dmibar_phys, size);
413
414 if (dmibar == NULL) {
415 perror("Error mapping DMIBAR");
416 exit(1);
417 }
418
419 printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys);
420 if (dmi_registers != NULL) {
421 for (i = 0; i < size; i++) {
422 switch (dmi_registers[i].size) {
423 case 4:
424 printf("dmibase+0x%04x: 0x%08x (%s)\n",
425 dmi_registers[i].addr,
426 read32(dmibar+dmi_registers[i].addr),
427 dmi_registers[i].name);
428 break;
429 case 2:
430 printf("dmibase+0x%04x: 0x%04x (%s)\n",
431 dmi_registers[i].addr,
432 read16(dmibar+dmi_registers[i].addr),
433 dmi_registers[i].name);
434 break;
435 case 1:
436 printf("dmibase+0x%04x: 0x%02x (%s)\n",
437 dmi_registers[i].addr,
438 read8(dmibar+dmi_registers[i].addr),
439 dmi_registers[i].name);
440 break;
441 }
442 }
443 } else {
444 for (i = 0; i < size; i += 4) {
445 if (read32(dmibar + i))
446 printf("0x%04x: 0x%08x\n", i, read32(dmibar+i));
447 }
448 }
449
450 unmap_physical((void *)dmibar, size);
451 return 0;
452 }
453
454 /*
455 * PCIe MMIO configuration space
456 */
457 int print_pciexbar(struct pci_dev *nb)
458 {
459 uint64_t pciexbar_reg;
460 uint64_t pciexbar_phys;
461 volatile uint8_t *pciexbar;
462 int max_busses, devbase, i;
463 int bus, dev, fn;
464
465 printf("========= PCIEXBAR ========\n\n");
466
467 switch (nb->device_id) {
468 case PCI_DEVICE_ID_INTEL_82915:
469 case PCI_DEVICE_ID_INTEL_82945GM:
470 case PCI_DEVICE_ID_INTEL_82945GSE:
471 case PCI_DEVICE_ID_INTEL_82945P:
472 case PCI_DEVICE_ID_INTEL_82975X:
473 pciexbar_reg = pci_read_long(nb, 0x48);
474 break;
475 case PCI_DEVICE_ID_INTEL_82946:
476 case PCI_DEVICE_ID_INTEL_82965PM:
477 case PCI_DEVICE_ID_INTEL_82Q965:
478 case PCI_DEVICE_ID_INTEL_82Q35:
479 case PCI_DEVICE_ID_INTEL_82G33:
480 case PCI_DEVICE_ID_INTEL_82Q33:
481 case PCI_DEVICE_ID_INTEL_82X38:
482 case PCI_DEVICE_ID_INTEL_32X0:
483 case PCI_DEVICE_ID_INTEL_82XX4X:
484 case PCI_DEVICE_ID_INTEL_82Q45:
485 case PCI_DEVICE_ID_INTEL_82G45:
486 case PCI_DEVICE_ID_INTEL_82G41:
487 case PCI_DEVICE_ID_INTEL_82B43:
488 case PCI_DEVICE_ID_INTEL_82B43_2:
489 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
490 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
491 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
492 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
493 case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
494 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
495 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
496 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
497 case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
498 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
499 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
500 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
501 case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
502 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
503 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D:
504 case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M:
505 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2:
506 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U:
507 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y:
508 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
509 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
510 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
511 case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E:
512 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
513 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
514 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
515 case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3:
516 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1:
517 case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2:
518 pciexbar_reg = pci_read_long(nb, 0x60);
519 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
520 break;
521 case PCI_DEVICE_ID_INTEL_82810:
522 case PCI_DEVICE_ID_INTEL_82810_DC:
523 case PCI_DEVICE_ID_INTEL_82810E_DC:
524 case PCI_DEVICE_ID_INTEL_82865:
525 printf("Error: This northbridge does not have PCIEXBAR.\n");
526 return 1;
527 default:
528 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
529 return 1;
530 }
531
532 if (!(pciexbar_reg & (1 << 0))) {
533 printf("PCIEXBAR register is disabled.\n");
534 return 0;
535 }
536
537 switch ((pciexbar_reg >> 1) & 3) {
538 case 0: // 256MB
539 pciexbar_phys = pciexbar_reg & (0xffULL << 28);
540 max_busses = 256;
541 break;
542 case 1: // 128M
543 pciexbar_phys = pciexbar_reg & (0x1ffULL << 27);
544 max_busses = 128;
545 break;
546 case 2: // 64M
547 pciexbar_phys = pciexbar_reg & (0x3ffULL << 26);
548 max_busses = 64;
549 break;
550 default: // RSVD
551 printf("Undefined address base. Bailing out.\n");
552 return 1;
553 }
554
555 printf("PCIEXBAR: 0x%08" PRIx64 "\n", pciexbar_phys);
556
557 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
558
559 if (pciexbar == NULL) {
560 perror("Error mapping PCIEXBAR");
561 exit(1);
562 }
563
564 for (bus = 0; bus < max_busses; bus++) {
565 for (dev = 0; dev < 32; dev++) {
566 for (fn = 0; fn < 8; fn++) {
567 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
568
569 if (read16(pciexbar + devbase) == 0xffff)
570 continue;
571
572 /* This is a heuristics. Anyone got a better check? */
573 if( (read32(pciexbar + devbase + 256) == 0xffffffff) &&
574 (read32(pciexbar + devbase + 512) == 0xffffffff) ) {
575 #if DEBUG
576 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
577 #endif
578 continue;
579 }
580
581 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
582 for (i = 0; i < 4096; i++) {
583 if((i % 0x10) == 0)
584 printf("\n%04x:", i);
585 printf(" %02x", *(pciexbar+devbase+i));
586 }
587 printf("\n");
588 }
589 }
590 }
591
592 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));
593
594 return 0;
595 }
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