util/inteltool/spi.c

   1
   2 #include <stdio.h>
   3 #include <stdlib.h>
   4 #include "inteltool.h"
   5
   6 static const io_register_t ich6_bios_cntl_registers[] = {
   7         { 0x0, 1, "BIOSWE - write enable" },
   8         { 0x1, 1, "BLE - lock enable" },
   9         { 0x2, 6, "reserved" },
  10 };
  11
  12 static const io_register_t ich7_bios_cntl_registers[] = {
  13         { 0x0, 1, "BIOSWE - write enable" },
  14         { 0x1, 1, "BLE - lock enable" },
  15         { 0x2, 2, "SPI Read configuration" },
  16         { 0x4, 1, "TopSwapStatus" },
  17         { 0x5, 3, "reserved" },
  18 };
  19
  20 static const io_register_t pch_bios_cntl_registers[] = {
  21         { 0x0, 1, "BIOSWE - write enable" },
  22         { 0x1, 1, "BLE - lock enable" },
  23         { 0x2, 2, "SPI Read configuration" },
  24         { 0x4, 1, "TopSwapStatus" },
  25         { 0x5, 1, "SMM BIOS Write Protect Disable" },
  26         { 0x6, 2, "reserved" },
  27 };
  28
  29 #define ICH9_SPIBAR 0x3800
  30 #define ICH78_SPIBAR 0x3020
  31
  32 static const io_register_t spi_bar_registers[] = {
  33         { 0x00, 4, "BFPR - BIOS Flash primary region" },
  34         { 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
  35         { 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
  36         { 0x08, 4, "FADDR - Flash Address" },
  37         { 0x0c, 4, "Reserved" },
  38         { 0x10, 4, "FDATA0" },
  39         /* 0x10 .. 0x4f are filled with data */
  40         { 0x50, 4, "FRACC - Flash Region Access Permissions" },
  41         { 0x54, 4, "Flash Region 0" },
  42         { 0x58, 4, "Flash Region 1" },
  43         { 0x5c, 4, "Flash Region 2" },
  44         { 0x60, 4, "Flash Region 3" },
  45         { 0x64, 4, "Flash Region 4" },
  46         { 0x74, 4, "FPR0 Flash Protected Range 0" },
  47         { 0x78, 4, "FPR0 Flash Protected Range 1" },
  48         { 0x7c, 4, "FPR0 Flash Protected Range 2" },
  49         { 0x80, 4, "FPR0 Flash Protected Range 3" },
  50         { 0x84, 4, "FPR0 Flash Protected Range 4" },
  51         { 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
  52         { 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
  53         { 0x94, 2, "PREOP - Prefix opcode Configuration" },
  54         { 0x96, 2, "OPTYPE - Opcode Type Configuration" },
  55         { 0x98, 8, "OPMENU - Opcode Menu Configuration" },
  56         { 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
  57         { 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
  58         { 0xb8, 4, "Reserved" },
  59         { 0xc0, 4, "AFC - Additional Flash Control" },
  60         { 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
  61         { 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
  62         { 0xd0, 4, "FPB - Flash Partition Boundary" },
  63 };
  64
  65 static const io_register_t ich7_spi_bar_registers[] = {
  66         { 0x00, 2, "SPIS - SPI Status" },
  67         { 0x02, 2, "SPIC - SPI Control" },
  68         { 0x04, 4, "SPIA - SPI Address" },
  69         /*
  70          *0x08 .. 0x47 are filled with data
  71          *0x48 .. 0x4f is not mentioned by datasheet
  72          */
  73         { 0x50, 4, "BBAR - BIOS Base Address Configuration" },
  74         { 0x54, 2, "PREOP Prefix Opcode Configuration" },
  75         { 0x56, 2, "OPTYPE Opcode Type Configuration" },
  76         { 0x58, 8, "OPMENU Opcode Menu Configuration" },
  77         { 0x60, 4, "PBR0 Protected BIOS Range 0" },
  78         { 0x64, 4, "PBR1 Protected BIOS Range 1" },
  79         { 0x68, 4, "PBR2 Protected BIOS Range 2" },
  80 };
  81
  82 static int print_bioscntl(struct pci_dev *sb)
  83 {
  84         int i, size = 0;
  85         unsigned char bios_cntl = 0xff;
  86         const io_register_t *bios_cntl_register = NULL;
  87
  88         printf("\n============= SPI / BIOS CNTL =============\n\n");
  89
  90         switch (sb->device_id) {
  91         case PCI_DEVICE_ID_INTEL_ICH6:
  92                 bios_cntl = pci_read_byte(sb, 0xdc);
  93                 bios_cntl_register = ich6_bios_cntl_registers;
  94                 size = ARRAY_SIZE(ich6_bios_cntl_registers);
  95                 break;
  96         case PCI_DEVICE_ID_INTEL_ICH7:
  97         case PCI_DEVICE_ID_INTEL_ICH7M:
  98         case PCI_DEVICE_ID_INTEL_ICH7DH:
  99         case PCI_DEVICE_ID_INTEL_ICH7MDH:
 100         case PCI_DEVICE_ID_INTEL_ICH8:
 101         case PCI_DEVICE_ID_INTEL_ICH8M:
 102         case PCI_DEVICE_ID_INTEL_ICH8ME:
 103         case PCI_DEVICE_ID_INTEL_ICH9DH:
 104         case PCI_DEVICE_ID_INTEL_ICH9DO:
 105         case PCI_DEVICE_ID_INTEL_ICH9R:
 106         case PCI_DEVICE_ID_INTEL_ICH9:
 107         case PCI_DEVICE_ID_INTEL_ICH9M:
 108         case PCI_DEVICE_ID_INTEL_ICH9ME:
 109         case PCI_DEVICE_ID_INTEL_ICH10:
 110         case PCI_DEVICE_ID_INTEL_ICH10D:
 111         case PCI_DEVICE_ID_INTEL_ICH10DO:
 112         case PCI_DEVICE_ID_INTEL_ICH10R:
 113         case PCI_DEVICE_ID_INTEL_NM10:
 114                 bios_cntl = pci_read_byte(sb, 0xdc);
 115                 bios_cntl_register = ich7_bios_cntl_registers;
 116                 size = ARRAY_SIZE(ich7_bios_cntl_registers);
 117                 break;
 118         case PCI_DEVICE_ID_INTEL_3400:
 119         case PCI_DEVICE_ID_INTEL_3420:
 120         case PCI_DEVICE_ID_INTEL_3450:
 121         case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
 122         case PCI_DEVICE_ID_INTEL_B55_A:
 123         case PCI_DEVICE_ID_INTEL_B55_B:
 124         case PCI_DEVICE_ID_INTEL_H55:
 125         case PCI_DEVICE_ID_INTEL_H57:
 126         case PCI_DEVICE_ID_INTEL_P55:
 127         case PCI_DEVICE_ID_INTEL_Q57:
 128         case PCI_DEVICE_ID_INTEL_3400_MOBILE:
 129         case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
 130         case PCI_DEVICE_ID_INTEL_HM55:
 131         case PCI_DEVICE_ID_INTEL_HM57:
 132         case PCI_DEVICE_ID_INTEL_PM55:
 133         case PCI_DEVICE_ID_INTEL_QM57:
 134         case PCI_DEVICE_ID_INTEL_QS57:
 135         case PCI_DEVICE_ID_INTEL_Z68:
 136         case PCI_DEVICE_ID_INTEL_P67:
 137         case PCI_DEVICE_ID_INTEL_UM67:
 138         case PCI_DEVICE_ID_INTEL_HM65:
 139         case PCI_DEVICE_ID_INTEL_H67:
 140         case PCI_DEVICE_ID_INTEL_HM67:
 141         case PCI_DEVICE_ID_INTEL_Q65:
 142         case PCI_DEVICE_ID_INTEL_QS67:
 143         case PCI_DEVICE_ID_INTEL_Q67:
 144         case PCI_DEVICE_ID_INTEL_QM67:
 145         case PCI_DEVICE_ID_INTEL_B65:
 146         case PCI_DEVICE_ID_INTEL_C202:
 147         case PCI_DEVICE_ID_INTEL_C204:
 148         case PCI_DEVICE_ID_INTEL_C206:
 149         case PCI_DEVICE_ID_INTEL_H61:
 150         case PCI_DEVICE_ID_INTEL_Z77:
 151         case PCI_DEVICE_ID_INTEL_Z75:
 152         case PCI_DEVICE_ID_INTEL_Q77:
 153         case PCI_DEVICE_ID_INTEL_Q75:
 154         case PCI_DEVICE_ID_INTEL_B75:
 155         case PCI_DEVICE_ID_INTEL_H77:
 156         case PCI_DEVICE_ID_INTEL_C216:
 157         case PCI_DEVICE_ID_INTEL_QM77:
 158         case PCI_DEVICE_ID_INTEL_QS77:
 159         case PCI_DEVICE_ID_INTEL_HM77:
 160         case PCI_DEVICE_ID_INTEL_UM77:
 161         case PCI_DEVICE_ID_INTEL_HM76:
 162         case PCI_DEVICE_ID_INTEL_HM75:
 163         case PCI_DEVICE_ID_INTEL_HM70:
 164         case PCI_DEVICE_ID_INTEL_NM70:
 165         case PCI_DEVICE_ID_INTEL_C8_MOBILE:
 166         case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
 167         case PCI_DEVICE_ID_INTEL_Z87:
 168         case PCI_DEVICE_ID_INTEL_Z85:
 169         case PCI_DEVICE_ID_INTEL_HM86:
 170         case PCI_DEVICE_ID_INTEL_H87:
 171         case PCI_DEVICE_ID_INTEL_HM87:
 172         case PCI_DEVICE_ID_INTEL_Q85:
 173         case PCI_DEVICE_ID_INTEL_Q87:
 174         case PCI_DEVICE_ID_INTEL_QM87:
 175         case PCI_DEVICE_ID_INTEL_B85:
 176         case PCI_DEVICE_ID_INTEL_C222:
 177         case PCI_DEVICE_ID_INTEL_C224:
 178         case PCI_DEVICE_ID_INTEL_C226:
 179         case PCI_DEVICE_ID_INTEL_H81:
 180         case PCI_DEVICE_ID_INTEL_C9_MOBILE:
 181         case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
 182         case PCI_DEVICE_ID_INTEL_HM97:
 183         case PCI_DEVICE_ID_INTEL_Z97:
 184         case PCI_DEVICE_ID_INTEL_H97:
 185         case PCI_DEVICE_ID_INTEL_H110:
 186         case PCI_DEVICE_ID_INTEL_H170:
 187         case PCI_DEVICE_ID_INTEL_Z170:
 188         case PCI_DEVICE_ID_INTEL_Q170:
 189         case PCI_DEVICE_ID_INTEL_Q150:
 190         case PCI_DEVICE_ID_INTEL_B150:
 191         case PCI_DEVICE_ID_INTEL_C236:
 192         case PCI_DEVICE_ID_INTEL_C232:
 193         case PCI_DEVICE_ID_INTEL_QM170:
 194         case PCI_DEVICE_ID_INTEL_HM170:
 195         case PCI_DEVICE_ID_INTEL_CM236:
 196         case PCI_DEVICE_ID_INTEL_HM175:
 197         case PCI_DEVICE_ID_INTEL_QM175:
 198         case PCI_DEVICE_ID_INTEL_CM238:
 199         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
 200         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
 201         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
 202         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
 203         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
 204         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
 205         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
 206         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
 207         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
 208         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
 209                 bios_cntl = pci_read_byte(sb, 0xdc);
 210                 bios_cntl_register = pch_bios_cntl_registers;
 211                 size = ARRAY_SIZE(pch_bios_cntl_registers);
 212                 break;
 213         default:
 214                 printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
 215                 return 1;
 216         }
 217
 218         printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl);
 219
 220         if (bios_cntl_register) {
 221                 for (i = 0; i < size; i++) {
 222                         unsigned int val = bios_cntl >> bios_cntl_register[i].addr;
 223                         val &= ((1 << bios_cntl_register[i].size) -1);
 224                         printf("0x%04x = %s\n", val, bios_cntl_register[i].name);
 225                 }
 226         }
 227
 228         return 0;
 229 }
 230
 231 static int print_spibar(struct pci_dev *sb) {
 232         int i, size = 0, rcba_size = 0x4000;
 233         volatile uint8_t *rcba;
 234         uint32_t rcba_phys;
 235         const io_register_t *spi_register = NULL;
 236         uint32_t spibaroffset;
 237
 238         printf("\n============= SPI Bar ==============\n\n");
 239
 240         switch (sb->device_id) {
 241         case PCI_DEVICE_ID_INTEL_ICH6:
 242                 printf("This southbridge does not have a SPI controller.\n");
 243                 return 1;
 244         case PCI_DEVICE_ID_INTEL_ICH7:
 245         case PCI_DEVICE_ID_INTEL_ICH7M:
 246         case PCI_DEVICE_ID_INTEL_ICH7DH:
 247         case PCI_DEVICE_ID_INTEL_ICH7MDH:
 248                 spibaroffset = ICH78_SPIBAR;
 249                 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
 250                 size = ARRAY_SIZE(ich7_spi_bar_registers);
 251                 spi_register = ich7_spi_bar_registers;
 252                 break;
 253         case PCI_DEVICE_ID_INTEL_ICH8:
 254                 spibaroffset = ICH78_SPIBAR;
 255                 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
 256                 size = ARRAY_SIZE(spi_bar_registers);
 257                 spi_register = spi_bar_registers;
 258                 break;
 259         case PCI_DEVICE_ID_INTEL_ICH8M:
 260         case PCI_DEVICE_ID_INTEL_ICH8ME:
 261         case PCI_DEVICE_ID_INTEL_ICH9DH:
 262         case PCI_DEVICE_ID_INTEL_ICH9DO:
 263         case PCI_DEVICE_ID_INTEL_ICH9R:
 264         case PCI_DEVICE_ID_INTEL_ICH9:
 265         case PCI_DEVICE_ID_INTEL_ICH9M:
 266         case PCI_DEVICE_ID_INTEL_ICH9ME:
 267         case PCI_DEVICE_ID_INTEL_ICH10:
 268         case PCI_DEVICE_ID_INTEL_ICH10D:
 269         case PCI_DEVICE_ID_INTEL_ICH10DO:
 270         case PCI_DEVICE_ID_INTEL_ICH10R:
 271         case PCI_DEVICE_ID_INTEL_NM10:
 272         case PCI_DEVICE_ID_INTEL_I63XX:
 273         case PCI_DEVICE_ID_INTEL_3400:
 274         case PCI_DEVICE_ID_INTEL_3420:
 275         case PCI_DEVICE_ID_INTEL_3450:
 276         case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
 277         case PCI_DEVICE_ID_INTEL_3400_MOBILE:
 278         case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
 279         case PCI_DEVICE_ID_INTEL_B55_A:
 280         case PCI_DEVICE_ID_INTEL_B55_B:
 281         case PCI_DEVICE_ID_INTEL_H55:
 282         case PCI_DEVICE_ID_INTEL_H57:
 283         case PCI_DEVICE_ID_INTEL_HM55:
 284         case PCI_DEVICE_ID_INTEL_HM57:
 285         case PCI_DEVICE_ID_INTEL_P55:
 286         case PCI_DEVICE_ID_INTEL_PM55:
 287         case PCI_DEVICE_ID_INTEL_Q57:
 288         case PCI_DEVICE_ID_INTEL_QM57:
 289         case PCI_DEVICE_ID_INTEL_QS57:
 290         case PCI_DEVICE_ID_INTEL_Z68:
 291         case PCI_DEVICE_ID_INTEL_P67:
 292         case PCI_DEVICE_ID_INTEL_UM67:
 293         case PCI_DEVICE_ID_INTEL_HM65:
 294         case PCI_DEVICE_ID_INTEL_H67:
 295         case PCI_DEVICE_ID_INTEL_HM67:
 296         case PCI_DEVICE_ID_INTEL_Q65:
 297         case PCI_DEVICE_ID_INTEL_QS67:
 298         case PCI_DEVICE_ID_INTEL_Q67:
 299         case PCI_DEVICE_ID_INTEL_QM67:
 300         case PCI_DEVICE_ID_INTEL_B65:
 301         case PCI_DEVICE_ID_INTEL_C202:
 302         case PCI_DEVICE_ID_INTEL_C204:
 303         case PCI_DEVICE_ID_INTEL_C206:
 304         case PCI_DEVICE_ID_INTEL_H61:
 305         case PCI_DEVICE_ID_INTEL_Z77:
 306         case PCI_DEVICE_ID_INTEL_Z75:
 307         case PCI_DEVICE_ID_INTEL_Q77:
 308         case PCI_DEVICE_ID_INTEL_Q75:
 309         case PCI_DEVICE_ID_INTEL_B75:
 310         case PCI_DEVICE_ID_INTEL_H77:
 311         case PCI_DEVICE_ID_INTEL_C216:
 312         case PCI_DEVICE_ID_INTEL_QM77:
 313         case PCI_DEVICE_ID_INTEL_QS77:
 314         case PCI_DEVICE_ID_INTEL_HM77:
 315         case PCI_DEVICE_ID_INTEL_UM77:
 316         case PCI_DEVICE_ID_INTEL_HM76:
 317         case PCI_DEVICE_ID_INTEL_HM75:
 318         case PCI_DEVICE_ID_INTEL_HM70:
 319         case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
 320         case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
 321         case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
 322         case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
 323         case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
 324         case PCI_DEVICE_ID_INTEL_C8_MOBILE:
 325         case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
 326         case PCI_DEVICE_ID_INTEL_Z87:
 327         case PCI_DEVICE_ID_INTEL_Z85:
 328         case PCI_DEVICE_ID_INTEL_HM86:
 329         case PCI_DEVICE_ID_INTEL_H87:
 330         case PCI_DEVICE_ID_INTEL_HM87:
 331         case PCI_DEVICE_ID_INTEL_Q85:
 332         case PCI_DEVICE_ID_INTEL_Q87:
 333         case PCI_DEVICE_ID_INTEL_QM87:
 334         case PCI_DEVICE_ID_INTEL_B85:
 335         case PCI_DEVICE_ID_INTEL_C222:
 336         case PCI_DEVICE_ID_INTEL_C224:
 337         case PCI_DEVICE_ID_INTEL_C226:
 338         case PCI_DEVICE_ID_INTEL_H81:
 339         case PCI_DEVICE_ID_INTEL_C9_MOBILE:
 340         case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
 341         case PCI_DEVICE_ID_INTEL_HM97:
 342         case PCI_DEVICE_ID_INTEL_Z97:
 343         case PCI_DEVICE_ID_INTEL_H97:
 344         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
 345         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
 346         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
 347         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
 348         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
 349         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
 350         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
 351         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
 352         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
 353         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
 354                 spibaroffset = ICH9_SPIBAR;
 355                 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
 356                 size = ARRAY_SIZE(spi_bar_registers);
 357                 spi_register = spi_bar_registers;
 358                 break;
 359         case PCI_DEVICE_ID_INTEL_ICH:
 360         case PCI_DEVICE_ID_INTEL_ICH0:
 361         case PCI_DEVICE_ID_INTEL_ICH2:
 362         case PCI_DEVICE_ID_INTEL_ICH4:
 363         case PCI_DEVICE_ID_INTEL_ICH4M:
 364         case PCI_DEVICE_ID_INTEL_ICH5:
 365                 printf("This southbridge does not have RCBA.\n");
 366                 return 1;
 367         default:
 368                 printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
 369                 return 1;
 370         }
 371
 372         rcba = map_physical(rcba_phys, rcba_size);
 373         if (rcba == NULL) {
 374                 perror("Error mapping RCBA");
 375                 exit(1);
 376         }
 377
 378         for (i = 0; i < size; i++) {
 379                 switch(spi_register[i].size) {
 380                         case 1:
 381                                 printf("0x%08x = %s\n", read8(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
 382                                 break;
 383                         case 2:
 384                                 printf("0x%08x = %s\n", read16(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
 385                                 break;
 386                         case 4:
 387                                 printf("0x%08x = %s\n", read32(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
 388                                 break;
 389                         case 8:
 390                                 printf("0x%08x%08x = %s\n",  read32(rcba + spibaroffset + spi_register[i].addr + 4),
 391                                         read32(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
 392                                 break;
 393                 }
 394         }
 395
 396         unmap_physical((void *)rcba, rcba_size);
 397         return 0;
 398 }
 399
 400 int print_spi(struct pci_dev *sb) {
 401         return (print_bioscntl(sb) || print_spibar(sb));
 402 }