cpu/x86/(sipi|smm): Pass on CR3 from ramstage
[coreboot2.git] / src / include / cpu / x86 / save_state.h
blob139a5fa7504b4e870c92a80b83a16b63a3c7f1f9
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __CPU_X86_SAVE_STATE_H__
4 #define __CPU_X86_SAVE_STATE_H__
6 #include <stdint.h>
8 enum cpu_reg {
9 RAX,
10 RBX,
11 RCX,
12 RDX
15 #define SMM_REV_INVALID 0xffffffff
17 struct smm_save_state_ops {
18 const uint32_t *revision_table;
19 /* Accessors for CPU registers in the SMM save state
20 Returns -1 on failure, 0 on success */
21 int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
22 int (*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length);
23 /* Returns -1 on failure, the node on which the 'cmd' was send on success */
24 int (*apmc_node)(u8 cmd);
27 /* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */
28 int get_apmc_node(u8 cmd);
29 /* Return -1 on failure, 0 on success.
30 Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */
31 int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
32 int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length);
34 #endif /* __CPU_X86_SAVE_STATE_H__ */