src/soc/intel/xeon_sp/chip_gen6.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpigen_pci.h>
   4 #include <assert.h>
   5 #include <device/pci.h>
   6 #include <intelblocks/acpi.h>
   7 #include <post.h>
   8 #include <soc/acpi.h>
   9 #include <soc/chip_common.h>
  10 #include <soc/numa.h>
  11 #include <soc/soc_util.h>
  12 #include <soc/util.h>
  13 #include <stdlib.h>
  14
  15 static const UDS_PCIROOT_RES *domain_to_pciroot_res(const struct device *dev)
  16 {
  17         assert(dev->path.type == DEVICE_PATH_DOMAIN);
  18         const union xeon_domain_path dn = {
  19                 .domain_path = dev_get_domain_id(dev)
  20         };
  21
  22         const IIO_UDS *hob = get_iio_uds();
  23         assert(hob != NULL);
  24
  25         const UDS_STACK_RES *sr = &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack];
  26         for (unsigned int index = 0; index < sr->PciRootBridgeNum; index++) {
  27                 if (sr->PciRoot[index].BusBase == dev->downstream->secondary)
  28                         return &sr->PciRoot[index];
  29         }
  30
  31         return NULL;
  32 }
  33
  34 static void iio_pci_domain_read_resources(struct device *dev)
  35 {
  36         int index = 0;
  37         const UDS_PCIROOT_RES *pr = domain_to_pciroot_res(dev);
  38
  39         /* Initialize the system-wide I/O space constraints. */
  40         if (pr->IoBase <= pr->IoLimit)
  41                 domain_io_window_from_to(dev, index++,
  42                         pr->IoBase, pr->IoLimit + 1);
  43
  44         /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */
  45         if (is_domain0(dev)) {
  46                 struct resource *res = new_resource(dev, index++);
  47                 res->base = 0;
  48                 res->limit = 0xfff;
  49                 res->size = 0x1000;
  50                 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  51         }
  52
  53         /* Initialize the system-wide memory resources constraints. */
  54         if (pr->Mmio32Base <= pr->Mmio32Limit)
  55                 domain_mem_window_from_to(dev, index++,
  56                         pr->Mmio32Base, pr->Mmio32Limit + 1);
  57
  58         /* Initialize the system-wide memory resources constraints. */
  59         if (pr->Mmio64Base <= pr->Mmio64Limit)
  60                 domain_mem_window_from_to(dev, index++,
  61                         pr->Mmio64Base, pr->Mmio64Limit + 1);
  62 }
  63
  64 static void iio_pci_domain_fill_ssdt(const struct device *domain)
  65 {
  66         soc_pci_domain_fill_ssdt(domain);
  67         pci_domain_fill_ssdt(domain);
  68 }
  69
  70 static struct device_operations iio_pcie_domain_ops = {
  71         .read_resources = iio_pci_domain_read_resources,
  72         .set_resources = pci_domain_set_resources,
  73         .scan_bus = pci_host_bridge_scan_bus,
  74 #if CONFIG(HAVE_ACPI_TABLES)
  75         .acpi_name = soc_acpi_name,
  76         .write_acpi_tables = northbridge_write_acpi_tables,
  77         .acpi_fill_ssdt = iio_pci_domain_fill_ssdt,
  78 #endif
  79 };
  80
  81 void create_xeonsp_domains(const union xeon_domain_path dp, struct bus *bus,
  82                                 const xSTACK_RES *sr, const size_t pci_segment_group)
  83 {
  84         for (unsigned int index = 0; index < sr->PciRootBridgeNum; index++) {
  85                 const UDS_PCIROOT_RES *pr = &sr->PciRoot[index];
  86                 create_domain(dp, bus,
  87                         pr->BusBase,
  88                         pr->BusLimit,
  89                         pciroot_res_to_domain_type(sr, pr),
  90                         &iio_pcie_domain_ops,
  91                         pci_segment_group);
  92         }
  93 }