1 ## SPDX-License-Identifier: GPL-2.0-only
5 config HAVE_VGA_TEXT_FRAMEBUFFER
7 depends on !(NO_GFX_INIT && NO_EARLY_GFX_INIT)
9 Selected by graphics drivers that support legacy VGA text mode.
11 config HAVE_VBE_LINEAR_FRAMEBUFFER
13 depends on !NO_GFX_INIT
15 Selected by graphics drivers that can set up a VBE linear-framebuffer
18 config HAVE_LINEAR_FRAMEBUFFER
20 depends on !NO_GFX_INIT
22 Selected by graphics drivers that can set up a generic linear
28 Selected by drivers that support to run a blob that implements
29 the Graphics Output Protocol (GOP).
31 config MAINBOARD_NO_FSP_GOP
34 Selected by mainboards that do not have any graphics ports connected to the SoC.
36 config MAINBOARD_HAS_NATIVE_VGA_INIT
39 Selected by mainboards / drivers that provide native graphics
42 config MAINBOARD_FORCE_NATIVE_VGA_INIT
44 depends on MAINBOARD_HAS_NATIVE_VGA_INIT || MAINBOARD_HAS_LIBGFXINIT
46 Selected by mainboards / chipsets whose graphics driver can't or
47 shouldn't be disabled.
49 config VGA_ROM_RUN_DEFAULT
52 Selected by mainboards whose graphics initialization depends on VGA OpROM.
53 coreboot needs to load/execute legacy VGA OpROM in order to initialize GFX.
55 config MAINBOARD_HAS_LIBGFXINIT
58 Selected by mainboards that implement support for `libgfxinit`.
59 Usually this requires a list of ports to be probed for displays.
61 config MAINBOARD_HAS_EARLY_LIBGFXINIT
64 Selected by mainboards that implement early (cache-as-ram
65 stage) support of `libgfxinit`. Usually this requires a list
66 of ports to be probed for displays.
69 prompt "Graphics initialization"
70 default NO_GFX_INIT if VGA_ROM_RUN_DEFAULT && PAYLOAD_SEABIOS
71 default VGA_ROM_RUN if VGA_ROM_RUN_DEFAULT
72 default MAINBOARD_DO_NATIVE_VGA_INIT
73 default MAINBOARD_USE_LIBGFXINIT
74 default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT
76 config MAINBOARD_DO_NATIVE_VGA_INIT
77 bool "Use native graphics init"
78 depends on MAINBOARD_HAS_NATIVE_VGA_INIT
80 Some mainboards, such as the Google Link, allow initializing the
81 display without the need of a binary only VGA OPROM. Enabling this
82 option may be faster, but also lacks flexibility in setting modes.
84 config MAINBOARD_USE_LIBGFXINIT
86 depends on MAINBOARD_HAS_LIBGFXINIT
87 select HAVE_VGA_TEXT_FRAMEBUFFER
88 select HAVE_LINEAR_FRAMEBUFFER
89 select VGA if VGA_TEXT_FRAMEBUFFER
91 Use the SPARK library `libgfxinit` for the native graphics
92 initialization. This requires an Ada toolchain.
94 # TODO: Explain differences (if any) for onboard cards.
96 bool "Run VGA Option ROMs"
97 depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT
98 select HAVE_VGA_TEXT_FRAMEBUFFER
100 Execute VGA Option ROMs in coreboot if found. This can be used
101 to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
104 When using a SeaBIOS payload it runs all option ROMs with much
105 more complete BIOS interrupt services available than coreboot,
106 which some option ROMs require in order to function correctly.
109 bool "Run a GOP driver"
110 depends on HAVE_FSP_GOP && !MAINBOARD_NO_FSP_GOP
111 select HAVE_LINEAR_FRAMEBUFFER
113 Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support
114 to run a GOP blob. This option enables graphics initialization with
119 depends on !MAINBOARD_FORCE_NATIVE_VGA_INIT
121 Select this to not perform any graphics initialization in
122 coreboot. This is useful if the payload (e.g. SeaBIOS) can
123 initialize graphics or if pre-boot graphics are not required.
128 prompt "Early (romstage) graphics initialization"
129 default MAINBOARD_USE_EARLY_LIBGFXINIT if MAINBOARD_HAS_EARLY_LIBGFXINIT
130 default NO_EARLY_GFX_INIT
132 config NO_EARLY_GFX_INIT
135 Select this to not perform any graphics initialization at
138 config MAINBOARD_USE_EARLY_LIBGFXINIT
139 bool "Use libgfxinit"
140 depends on MAINBOARD_HAS_EARLY_LIBGFXINIT
143 Use the SPARK library `libgfxinit` for the romstage native
144 graphics initialization. This requires an Ada
145 toolchain. Graphics at romstage is limited to VGA text mode.
149 config PRE_GRAPHICS_DELAY_MS
150 int "Graphics initialization delay in ms"
152 depends on VGA_ROM_RUN
154 On some systems, coreboot boots so fast that connected monitors
155 (mostly TVs) won't be able to wake up fast enough to talk to the
156 VBIOS. On those systems we need to wait for a bit before executing
159 config ONBOARD_VGA_IS_PRIMARY
160 bool "Use onboard VGA as primary video device"
164 This option lets you select which VGA device will be used
165 to decode legacy VGA cycles. Not all chipsets implement this
166 however. If not selected, the last adapter found will be used,
167 else the onboard adapter is used.
169 config S3_VGA_ROM_RUN
170 bool "Re-run VGA Option ROMs on S3 resume"
172 depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
174 Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
176 When using a SeaBIOS payload it runs all option ROMs with much
177 more complete BIOS interrupt services available than coreboot,
178 which some option ROMs require in order to function correctly.
180 If unsure, say N when using SeaBIOS as payload, Y otherwise.
182 config ALWAYS_LOAD_OPROM
184 depends on VGA_ROM_RUN
186 Always load option ROMs if any are found. The decision to run
187 the ROM is still determined at runtime, but the distinction
188 between loading and not running comes into play for CHROMEOS.
190 An example where this is required is that VBT (Video BIOS Tables)
191 are needed for the kernel's display driver to know how a piece of
192 hardware is configured to be used.
194 config ALWAYS_RUN_OPROM
196 depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM
198 Always unconditionally run the option regardless of other
201 config ON_DEVICE_ROM_LOAD
202 bool "Load Option ROMs on PCI devices"
203 default n if PAYLOAD_SEABIOS
204 default y if !PAYLOAD_SEABIOS
205 depends on VGA_ROM_RUN
207 Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.
209 If disabled, only Option ROMs stored in CBFS will be executed by
210 coreboot. If you are concerned about security, you might want to
211 disable this option, but it might leave your system in a state of
212 degraded functionality.
214 When using a SeaBIOS payload it runs all option ROMs with much
215 more complete BIOS interrupt services available than coreboot,
216 which some option ROMs require in order to function correctly.
218 If unsure, say N when using SeaBIOS as payload, Y otherwise.
221 prompt "Option ROM execution type"
222 default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
223 default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86
224 depends on VGA_ROM_RUN
226 config PCI_OPTION_ROM_RUN_REALMODE
229 depends on ARCH_X86 && !ARCH_RAMSTAGE_X86_64
231 If you select this option, PCI Option ROMs will be executed
232 natively on the CPU in real mode. No CPU emulation is involved,
233 so this is the fastest, but also the least secure option.
234 (only works on x86/x64 systems)
236 config PCI_OPTION_ROM_RUN_YABEL
240 If you select this option, the x86emu CPU emulator will be used to
241 execute PCI Option ROMs.
243 This option prevents Option ROMs from doing dirty tricks with the
244 system (such as installing SMM modules or hypervisors), but it is
245 also significantly slower than the native Option ROM initialization
248 This is the default choice for non-x86 systems.
252 config YABEL_PCI_ACCESS_OTHER_DEVICES
253 prompt "Allow Option ROMs to access other devices"
255 depends on PCI_OPTION_ROM_RUN_YABEL
257 Per default, YABEL only allows Option ROMs to access the PCI device
258 that they are associated with. However, this causes trouble for some
259 onboard graphics chips whose Option ROM needs to reconfigure the
262 config YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG
263 prompt "Fake success on writing other device's config space"
265 depends on YABEL_PCI_ACCESS_OTHER_DEVICES
267 By default, YABEL aborts when the Option ROM tries to write to other
268 devices' config spaces. With this option enabled, the write doesn't
269 follow through, but the Option ROM is allowed to go on.
270 This can create issues such as hanging Option ROMs (if it depends on
271 that other register changing to the written value), so test for
272 impact before using this option.
274 config YABEL_VIRTMEM_LOCATION
275 prompt "Location of YABEL's virtual memory"
277 depends on PCI_OPTION_ROM_RUN_YABEL
280 YABEL requires 1MB memory for its CPU emulation. This memory is
281 normally located at 16MB.
283 config YABEL_DIRECTHW
284 prompt "Direct hardware access"
286 depends on PCI_OPTION_ROM_RUN_YABEL && ARCH_X86
288 YABEL consists of two parts: It uses x86emu for the CPU emulation and
289 additionally provides a PC system emulation that filters bad device
290 and memory access (such as PCI config space access to other devices
291 than the initialized one).
293 When choosing this option, x86emu will pass through all hardware
294 accesses to memory and I/O devices to the underlying memory and I/O
295 addresses. While this option prevents Option ROMs from doing dirty
296 tricks with the CPU (such as installing SMM modules or hypervisors),
297 they can still access all devices in the system.
298 Enable this option for a good compromise between security and speed.
301 depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
303 config FRAMEBUFFER_SET_VESA_MODE
304 prompt "Set framebuffer graphics resolution"
306 default y if CHROMEOS
307 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
308 select HAVE_VBE_LINEAR_FRAMEBUFFER
310 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
312 if FRAMEBUFFER_SET_VESA_MODE
315 prompt "framebuffer graphics resolution"
316 default FRAMEBUFFER_VESA_MODE_118
318 This option sets the resolution used for the coreboot framebuffer (and
321 config FRAMEBUFFER_VESA_MODE_100
322 bool "640x400 256-color"
324 config FRAMEBUFFER_VESA_MODE_101
325 bool "640x480 256-color"
327 config FRAMEBUFFER_VESA_MODE_102
328 bool "800x600 16-color"
330 config FRAMEBUFFER_VESA_MODE_103
331 bool "800x600 256-color"
333 config FRAMEBUFFER_VESA_MODE_104
334 bool "1024x768 16-color"
336 config FRAMEBUFFER_VESA_MODE_105
337 bool "1024x768 256-color"
339 config FRAMEBUFFER_VESA_MODE_106
340 bool "1280x1024 16-color"
342 config FRAMEBUFFER_VESA_MODE_107
343 bool "1280x1024 256-color"
345 config FRAMEBUFFER_VESA_MODE_108
348 config FRAMEBUFFER_VESA_MODE_109
351 config FRAMEBUFFER_VESA_MODE_10A
354 config FRAMEBUFFER_VESA_MODE_10B
357 config FRAMEBUFFER_VESA_MODE_10C
360 config FRAMEBUFFER_VESA_MODE_10D
361 bool "320x200 32k-color (1:5:5:5)"
363 config FRAMEBUFFER_VESA_MODE_10E
364 bool "320x200 64k-color (5:6:5)"
366 config FRAMEBUFFER_VESA_MODE_10F
367 bool "320x200 16.8M-color (8:8:8)"
369 config FRAMEBUFFER_VESA_MODE_110
370 bool "640x480 32k-color (1:5:5:5)"
372 config FRAMEBUFFER_VESA_MODE_111
373 bool "640x480 64k-color (5:6:5)"
375 config FRAMEBUFFER_VESA_MODE_112
376 bool "640x480 16.8M-color (8:8:8)"
378 config FRAMEBUFFER_VESA_MODE_113
379 bool "800x600 32k-color (1:5:5:5)"
381 config FRAMEBUFFER_VESA_MODE_114
382 bool "800x600 64k-color (5:6:5)"
384 config FRAMEBUFFER_VESA_MODE_115
385 bool "800x600 16.8M-color (8:8:8)"
387 config FRAMEBUFFER_VESA_MODE_116
388 bool "1024x768 32k-color (1:5:5:5)"
390 config FRAMEBUFFER_VESA_MODE_117
391 bool "1024x768 64k-color (5:6:5)"
393 config FRAMEBUFFER_VESA_MODE_118
394 bool "1024x768 16.8M-color (8:8:8)"
396 config FRAMEBUFFER_VESA_MODE_119
397 bool "1280x1024 32k-color (1:5:5:5)"
399 config FRAMEBUFFER_VESA_MODE_11A
400 bool "1280x1024 64k-color (5:6:5)"
402 config FRAMEBUFFER_VESA_MODE_11B
403 bool "1280x1024 16.8M-color (8:8:8)"
405 config FRAMEBUFFER_VESA_MODE_USER
406 bool "Manually select VESA mode"
410 # Map the config names to an integer (KB).
411 config FRAMEBUFFER_VESA_MODE
412 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
414 default 0x100 if FRAMEBUFFER_VESA_MODE_100
415 default 0x101 if FRAMEBUFFER_VESA_MODE_101
416 default 0x102 if FRAMEBUFFER_VESA_MODE_102
417 default 0x103 if FRAMEBUFFER_VESA_MODE_103
418 default 0x104 if FRAMEBUFFER_VESA_MODE_104
419 default 0x105 if FRAMEBUFFER_VESA_MODE_105
420 default 0x106 if FRAMEBUFFER_VESA_MODE_106
421 default 0x107 if FRAMEBUFFER_VESA_MODE_107
422 default 0x108 if FRAMEBUFFER_VESA_MODE_108
423 default 0x109 if FRAMEBUFFER_VESA_MODE_109
424 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
425 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
426 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
427 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
428 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
429 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
430 default 0x110 if FRAMEBUFFER_VESA_MODE_110
431 default 0x111 if FRAMEBUFFER_VESA_MODE_111
432 default 0x112 if FRAMEBUFFER_VESA_MODE_112
433 default 0x113 if FRAMEBUFFER_VESA_MODE_113
434 default 0x114 if FRAMEBUFFER_VESA_MODE_114
435 default 0x115 if FRAMEBUFFER_VESA_MODE_115
436 default 0x116 if FRAMEBUFFER_VESA_MODE_116
437 default 0x117 if FRAMEBUFFER_VESA_MODE_117
438 default 0x118 if FRAMEBUFFER_VESA_MODE_118
439 default 0x119 if FRAMEBUFFER_VESA_MODE_119
440 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
441 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
442 default 0x118 if FRAMEBUFFER_VESA_MODE_USER
443 endif # FRAMEBUFFER_SET_VESA_MODE
445 config WANT_LINEAR_FRAMEBUFFER
447 default y if CHROMEOS
448 default y if PAYLOAD_EDK2
449 default y if COREDOOM_SECONDARY_PAYLOAD
452 prompt "Framebuffer mode"
453 default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER
454 default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER
455 default VGA_TEXT_FRAMEBUFFER
457 config VGA_TEXT_FRAMEBUFFER
458 bool "Legacy VGA text mode"
459 depends on HAVE_VGA_TEXT_FRAMEBUFFER
461 If this option is enabled, coreboot will initialize graphics in
462 legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,
463 switch to text mode before handing control to a payload.
465 config VBE_LINEAR_FRAMEBUFFER
466 bool "VESA framebuffer"
467 depends on HAVE_VBE_LINEAR_FRAMEBUFFER
469 This option keeps the framebuffer mode set after coreboot finishes
470 execution. If this option is enabled, coreboot will pass a
471 framebuffer entry in its coreboot table and the payload will need a
474 config GENERIC_LINEAR_FRAMEBUFFER
475 bool "Linear \"high-resolution\" framebuffer"
476 depends on HAVE_LINEAR_FRAMEBUFFER
478 This option enables a high-resolution, linear framebuffer. If this
479 option is enabled, coreboot will pass a framebuffer entry in its
480 coreboot table and the payload will need a compatible driver.
484 # Workaround to have LINEAR_FRAMEBUFFER set in both cases
485 # VBE_LINEAR_FRAMEBUFFER and GENERIC_LINEAR_FRAMEBUFFER.
486 # `kconfig_lint` doesn't let us use the same name with
487 # different texts in the choice above.
488 config LINEAR_FRAMEBUFFER
490 depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER
493 prompt "Show graphical bootsplash"
495 depends on LINEAR_FRAMEBUFFER
497 This option shows a graphical bootsplash screen. The graphics are
498 loaded from the CBFS file bootsplash.jpg.
500 You can either specify the location and file name of the
501 image in the 'General' section or add it manually to CBFS, using,
502 for example, cbfstool.
504 config LINEAR_FRAMEBUFFER_MAX_WIDTH
505 int "Maximum width in pixels"
506 depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT
507 default 2560 if SYSTEM_TYPE_LAPTOP
510 Set the maximum width of the framebuffer. This may help with
511 default fonts too tiny for high-resolution displays.
513 config LINEAR_FRAMEBUFFER_MAX_HEIGHT
514 int "Maximum height in pixels"
515 depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT
516 default 1600 if SYSTEM_TYPE_LAPTOP
519 Set the maximum height of the framebuffer. This may help with
520 default fonts too tiny for high-resolution displays.
530 config DOMAIN_RESOURCE_32BIT_LIMIT
534 When the default pci_domain_read_resources() is used,
535 keep 32-bit memory resources below this limit. This is
536 used as a workaround for missing/wrong reservations of
537 chipset resources that usually reside above this limit.
539 config NO_ECAM_MMCONF_SUPPORT
543 Disable the use of the Enhanced Configuration
544 Access mechanism (ECAM) method for accessing PCI config
547 config ECAM_MMCONF_SUPPORT
549 default !NO_ECAM_MMCONF_SUPPORT
551 Enable the use of the Enhanced Configuration
552 Access mechanism (ECAM) method for accessing PCI config
555 config PCIX_PLUGIN_SUPPORT
559 config CARDBUS_PLUGIN_SUPPORT
563 config AZALIA_HDA_CODEC_SUPPORT
567 Select this option to include the code to initialize Azalia HD audio
568 codec chips. This will also add the hda_verb.c file from the
569 mainboard directory to the build which contain the board-specific HD
570 audio codec configuration.
572 config AZALIA_LOCK_DOWN_R_WO_GCAP
574 depends on AZALIA_HDA_CODEC_SUPPORT
576 The GCAP register is implemented as R/WO (Read / Write Once) on some
577 HD Audio controllers, such as Intel 6-series PCHs. Select this option
578 to lock down the GCAP register after deasserting the controller reset
579 bit. Locking is done by reading GCAP and writing back the read value.
581 config PCIEXP_PLUGIN_SUPPORT
585 config ECAM_MMCONF_BASE_ADDRESS
587 depends on ECAM_MMCONF_SUPPORT
589 config ECAM_MMCONF_BUS_NUMBER
591 depends on ECAM_MMCONF_SUPPORT
593 Total number of PCI buses in the system across all segment groups.
594 The number needs to be a power of 2. For values <= 256,
595 PCI_BUSES_PER_SEGMENT_GROUP is CONFIG_ECAM_MMCONF_BUS_NUMBER and
596 PCI_SEGMENT_GROUP_COUNT is 1. For values > 256,
597 PCI_BUSES_PER_SEGMENT_GROUP is 256 and PCI_SEGMENT_GROUP_COUNT is
598 CONFIG_ECAM_MMCONF_BUS_NUMBER / 256.
600 config ECAM_MMCONF_LENGTH
602 depends on ECAM_MMCONF_SUPPORT
603 default 0x02000000 if ECAM_MMCONF_BUS_NUMBER = 32
604 default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64
605 default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128
606 default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256
607 default 0x20000000 if ECAM_MMCONF_BUS_NUMBER = 512
608 default 0x80000000 if ECAM_MMCONF_BUS_NUMBER = 1024
611 config PCI_ALLOW_BUS_MASTER
612 bool "Allow coreboot to set optional PCI bus master bits"
615 For security reasons, bus mastering should be enabled as late as
616 possible. In coreboot, it's usually not necessary and payloads
617 should only enable it for devices they use. Since not all payloads
618 enable bus mastering properly yet, this option gives some sort of
619 "backwards compatibility" and is enabled by default to keep the
620 traditional behaviour for now. This is currently necessary, for
621 instance, for libpayload based payloads as the drivers don't enable
622 bus mastering for PCI bridges.
624 if PCI_ALLOW_BUS_MASTER
626 config PCI_SET_BUS_MASTER_PCI_BRIDGES
630 Let coreboot configure bus mastering for PCI bridges. Enabling bus
631 mastering for a PCI bridge also allows it to forward requests from
632 downstream devices. Currently, payloads ignore this and only enable
633 bus mastering for the downstream device. Hence, this option is needed
634 for compatibility until payloads are fixed.
636 config PCI_ALLOW_BUS_MASTER_ANY_DEVICE
639 select PCI_SET_BUS_MASTER_PCI_BRIDGES
641 Allow coreboot to enable PCI bus mastering for any device. The actual
642 selection of devices depends on the various PCI drivers in coreboot.
644 endif # PCI_ALLOW_BUS_MASTER
648 if PCIEXP_PLUGIN_SUPPORT
650 config PCIEXP_COMMON_CLOCK
651 prompt "Enable PCIe Common Clock"
655 Detect and enable Common Clock on PCIe links.
658 prompt "Enable PCIe ASPM"
662 Detect and enable ASPM (Active State Power Management) on PCIe links.
665 prompt "Enable PCIe Clock Power Management"
669 Detect and enable Clock Power Management on PCIe.
671 config PCIEXP_L1_SUB_STATE
672 prompt "Enable PCIe ASPM L1 SubState"
674 depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
677 Detect and enable ASPM on PCIe links.
679 config PCIEXP_SUPPORT_RESIZABLE_BARS
680 prompt "Support PCIe Resizable BARs"
682 depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
685 When enabled, this will check PCIe devices for Resizable BAR support,
686 and if found, will use this to discover the preferred BAR sizes of
687 the device in preference over the traditional moving bits method. The
688 amount of address space given out to devices in this manner (since
689 it can range up to 8 EB) can be limited with the
690 PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS Kconfig setting below.
692 if PCIEXP_SUPPORT_RESIZABLE_BARS
694 config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
695 int "Bits of address space to give to Resizable BARs"
696 range 20 63 # 1 MiB - 8 EiB
699 This is the maximum number of bits of address space to allocate for
700 PCIe devices with resizable BARs. For instance, if a device requests
701 30 bits of address space (1 GiB), but this field is set to 29, then
702 the device will only be allocated 29 bits worth of address space (512
703 MiB). Valid values range from 20 (1 MiB) to 63 (8 EiB); these come
704 from the Resizable BAR portion of the PCIe spec (7.8.6).
706 endif # PCIEXP_SUPPORT_RESIZABLE_BARS
708 config PCIEXP_LANE_ERR_STAT_CLEAR
709 prompt "Enable Clear PCIe Lane Error Status"
713 Clear the PCIe Lane Error Status at the end of link training.
715 config PCIEXP_HOTPLUG
716 prompt "Enable PCIe Hotplug Support"
720 Allocate resources for PCIe hotplug bridges
724 config PCIEXP_HOTPLUG_BUSES
725 int "PCI Express Hotplug Buses"
728 This is the number of buses allocated for hotplug PCI express
729 bridges, for use by hotplugged child devices. The default is 8
732 config PCIEXP_HOTPLUG_MEM
733 hex "PCI Express Hotplug Memory"
736 This is the amount of memory space, in bytes, to allocate to
737 hotplug PCI express bridges, for use by hotplugged child devices.
738 This size should be page-aligned. The default is 8 MiB.
740 config PCIEXP_HOTPLUG_PREFETCH_MEM
741 hex "PCI Express Hotplug Prefetch Memory"
744 This is the amount of pre-fetchable memory space, in bytes, to
745 allocate to hot-plug PCI express bridges, for use by hotplugged
746 child devices. This size should be page-aligned. The default is
749 config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G
751 default y if !PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
754 This enables prefetch memory allocation above 4G boundary for the
757 config PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
758 bool "PCI Express Hotplug Prefetch Memory Allocation below 4G boundary"
761 This enables prefetch memory allocation below 4G boundary for the
764 config PCIEXP_HOTPLUG_IO
765 hex "PCI Express Hotplug I/O Space"
768 This is the amount of I/O space to allocate to hot-plug PCI
769 express bridges, for use by hotplugged child devices. The default
772 endif # PCIEXP_HOTPLUG
774 endif # PCIEXP_PLUGIN_SUPPORT
776 config EARLY_PCI_BRIDGE
777 bool "Early PCI bridge"
781 While coreboot is executing code from ROM, the coreboot resource
782 allocator has not been running yet. Hence PCI devices living behind
783 a bridge are not yet visible to the system.
785 This option enables static configuration for a single pre-defined
786 PCI bridge function on bus 0.
790 config EARLY_PCI_BRIDGE_DEVICE
794 config EARLY_PCI_BRIDGE_FUNCTION
795 hex "bridge function"
798 config EARLY_PCI_MMIO_BASE
799 hex "MMIO window base"
802 endif # EARLY_PCI_BRIDGE
804 config SUBSYSTEM_VENDOR_ID
805 hex "Override PCI Subsystem Vendor ID"
809 This config option will override the devicetree settings for
810 PCI Subsystem Vendor ID.
812 Note: This option is not meant for a board's Kconfig; use the
813 devicetree setting `subsystemid` instead.
815 config SUBSYSTEM_DEVICE_ID
816 hex "Override PCI Subsystem Device ID"
820 This config option will override the devicetree settings for
821 PCI Subsystem Device ID.
823 Note: This option is not meant for a board's Kconfig; use the
824 devicetree setting `subsystemid` instead.
827 bool "Add a VGA BIOS image"
829 select VGA_ROM_RUN_DEFAULT
831 Select this option if you have a VGA BIOS image that you would
832 like to add to your ROM.
834 You will be able to specify the location and file name of the
838 string "VGA BIOS path and filename"
840 default "vgabios.bin"
842 The path and filename of the file to use as VGA BIOS.
845 string "VGA device PCI IDs"
849 The comma-separated PCI vendor and device ID that would associate
850 your vBIOS to your video card.
854 In the above example 1106 is the PCI vendor ID (in hex, but without
855 the "0x" prefix) and 3230 specifies the PCI device ID of the
856 video card (also in hex, without "0x" prefix).
858 This ID needs to match the PCI VID and DID in the VGA BIOS file's
859 header and also needs to match the value returned by map_oprom_vendev
860 if the remapping feature is used.
862 Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
864 config VGA_BIOS_SECOND
865 bool "Add a 2nd video BIOS image"
866 depends on ARCH_X86 && VGA_BIOS
868 Select this option if you have a 2nd video BIOS image that you would
869 like to add to your ROM.
871 config VGA_BIOS_SECOND_FILE
872 string "2nd video BIOS path and filename"
873 depends on VGA_BIOS_SECOND
876 The path and filename of the file to use as video BIOS.
878 config VGA_BIOS_SECOND_ID
879 string "Graphics device PCI IDs"
880 depends on VGA_BIOS_SECOND
882 The comma-separated PCI vendor and device ID that would associate
883 your vBIOS to your video card.
887 In the above example 1106 is the PCI vendor ID (in hex, but without
888 the "0x" prefix) and 3230 specifies the PCI device ID of the
889 video card (also in hex, without "0x" prefix).
891 Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
894 bool "Add a discrete VGA BIOS image"
897 Select this option if you have a VGA BIOS image for discrete GPU
898 that you would like to add to your ROM.
900 You will be able to specify the location and file name of the
903 config VGA_BIOS_DGPU_FILE
904 string "Discrete VGA BIOS path and filename"
905 depends on VGA_BIOS_DGPU
906 default "vgabios_dgpu.bin"
908 The path and filename of the file to use as VGA BIOS for discrete GPU.
910 config VGA_BIOS_DGPU_ID
911 string "Discrete VGA device PCI IDs"
912 depends on VGA_BIOS_DGPU
915 The comma-separated PCI vendor and device ID that would associate
916 your VGA BIOS to your discrete video card.
919 1002,6663 for HD 8570M
920 1002,6665 for R5 M230
922 In the above examples 1002 is the PCI vendor ID (in hex, but without
923 the "0x" prefix) and 6663 / 6665 specifies the PCI device ID of the
924 discrete video card (also in hex, without "0x" prefix).
926 Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
928 config INTEL_GMA_HAVE_VBT
931 Select this in the mainboard Kconfig to indicate the board has
934 config INTEL_GMA_ADD_VBT
935 depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON
936 bool "Add a Video BIOS Table (VBT) binary to CBFS"
937 default y if INTEL_GMA_HAVE_VBT
939 Add a VBT data file to CBFS. The VBT describes the integrated
940 GPU and connections, and is needed by the GOP driver integrated into
941 FSP and the OS driver in order to initialize the display.
943 config INTEL_GMA_VBT_FILE
944 string "VBT binary path and filename"
945 depends on INTEL_GMA_ADD_VBT
946 default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(VARIANT_DIR)/data.vbt" \
947 if INTEL_GMA_HAVE_VBT && VARIANT_DIR != ""
948 default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if INTEL_GMA_HAVE_VBT
949 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/vbt.bin"
951 The path and filename of the VBT binary.
954 bool "Enable I2C controller emulation in software"
957 This config option will enable code to override the i2c_transfer
958 routine with a (simple) software emulation of the protocol. This may
959 be useful for debugging or on platforms where a driver for the real
960 I2C controller is not (yet) available. The platform code needs to
961 provide bindings to manually toggle I2C lines.
963 config I2C_TRANSFER_TIMEOUT_US
964 int "I2C transfer timeout in microseconds"
967 Timeout for a read/write transfers on the I2C bus, that is, the
968 maximum time a device could stretch clock bits before the transfer
969 is aborted and an error returned.
971 config RESOURCE_ALLOCATION_TOP_DOWN
972 bool "Allocate resources from top down"
973 default n if PAYLOAD_EDK2
976 Top-down allocation is required to place resources above 4G by
977 default (i.e. even when there is still space below). On some
978 platforms, it might make a difference because of conflicts with
979 undeclared resources. EDK2 is currently reported to also have
980 problems on some platforms, at least with Intel's IGD.
982 config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION
984 default n if ARCH_X86
987 Don't limit mem resources to 4G, but to their actual limit.
992 Provides xHCI utility functions.
994 config D3COLD_SUPPORT
998 Enable this option if all devices on your system support the
999 D3Cold power management state. The D3Cold state is a low-power
1000 state where the device has been powered down and is no longer
1001 able to maintain its context. This state can help reduce
1002 overall system power consumption, which can be beneficial for
1003 energy savings and thermal management.
1005 Please note that enabling D3Cold support may break system
1006 suspend-to-RAM (S3) functionality.
1008 source "src/device/dram/Kconfig"