src/include/cpu/intel/em64t101_save_state.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __EM64T101_SAVE_STATE_H__
   4 #define __EM64T101_SAVE_STATE_H__
   5
   6 #include <types.h>
   7 #include <cpu/x86/smm.h>
   8
   9 /* Intel Revision 30101 SMM State-Save Area
  10  * The following processor architectures use this:
  11  * - Westmere
  12  * - SandyBridge
  13  * - IvyBridge
  14  * - Haswell
  15  */
  16 #define SMM_EM64T101_ARCH_OFFSET 0x7c00
  17 #define SMM_EM64T101_SAVE_STATE_OFFSET \
  18         SMM_SAVE_STATE_BEGIN(SMM_EM64T101_ARCH_OFFSET)
  19 typedef struct {
  20         u8      reserved0[256];
  21         u8      reserved1[208];
  22
  23         u32     gdtr_upper_base;
  24         u32     ldtr_upper_base;
  25         u32     idtr_upper_base;
  26
  27         u32     io_cf8;
  28
  29         u64     io_rdi;
  30         u64     io_rip;
  31         u64     io_rcx;
  32         u64     io_rsi;
  33
  34         u8      reserved2[52];
  35         u32     shutdown_auto_restart;
  36         u8      reserved3[8];
  37         u32     cr4;
  38
  39         u8      reserved4[72];
  40
  41         u32     gdtr_base;
  42         u8      reserved5[4];
  43         u32     idtr_base;
  44         u8      reserved6[4];
  45         u32     ldtr_base;
  46
  47         u8      reserved7[56];
  48         /* EPTP fields are only on Haswell according to BWGs, but Intel was
  49          * wise and reused the same revision number. */
  50         u64     eptp;
  51         u32     eptp_en;
  52         u32     cs_base;
  53         u8      reserved8[4];
  54         u32     iedbase;
  55
  56         u8      reserved9[8];
  57
  58         u32     smbase;
  59         u32     smm_revision;
  60
  61         u16     io_restart;
  62         u16     autohalt_restart;
  63
  64         u8      reserved10[24];
  65
  66         u64     r15;
  67         u64     r14;
  68         u64     r13;
  69         u64     r12;
  70         u64     r11;
  71         u64     r10;
  72         u64     r9;
  73         u64     r8;
  74
  75         u64     rax;
  76         u64     rcx;
  77         u64     rdx;
  78         u64     rbx;
  79
  80         u64     rsp;
  81         u64     rbp;
  82         u64     rsi;
  83         u64     rdi;
  84
  85         u64     io_mem_addr;
  86         u32     io_misc_info;
  87
  88         u32     es_sel;
  89         u32     cs_sel;
  90         u32     ss_sel;
  91         u32     ds_sel;
  92         u32     fs_sel;
  93         u32     gs_sel;
  94
  95         u32     ldtr_sel;
  96         u32     tr_sel;
  97
  98         u64     dr7;
  99         u64     dr6;
 100         u64     rip;
 101         u64     efer;
 102         u64     rflags;
 103
 104         u64     cr3;
 105         u64     cr0;
 106 } __packed em64t101_smm_state_save_area_t;
 107
 108 #endif