src/soc/amd/picasso/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __PICASSO_CHIP_H__
   4 #define __PICASSO_CHIP_H__
   5
   6 #include <amdblocks/chip.h>
   7 #include <amdblocks/pci_clk_req.h>
   8 #include <commonlib/helpers.h>
   9 #include <drivers/i2c/designware/dw_i2c.h>
  10 #include <gpio.h>
  11 #include <soc/i2c.h>
  12 #include <soc/iomap.h>
  13 #include <soc/southbridge.h>
  14 #include <arch/x86/include/arch/smp/mpspec.h> /* point from top level */
  15 #include <types.h>
  16
  17 /*
  18   USB 2.0 PHY Parameters
  19 */
  20 struct __packed usb2_phy_tune {
  21         /* Disconnect Threshold Adjustment. Range 0 - 0x7 */
  22         uint8_t com_pds_tune;
  23         /* Squelch Threshold Adjustment. Range 0 - 0x7 */
  24         uint8_t sq_rx_tune;
  25         /* FS/LS Source Impedance Adjustment. Range 0 - 0xF */
  26         uint8_t tx_fsls_tune;
  27         /* HS Transmitter Pre-Emphasis Current Control. Range 0 - 0x3 */
  28         uint8_t tx_pre_emp_amp_tune;
  29         /* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */
  30         uint8_t tx_pre_emp_pulse_tune;
  31         /* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */
  32         uint8_t tx_rise_tune;
  33         /* HS DC Voltage Level Adjustment. Range 0 - 0xF */
  34         uint8_t tx_vref_tune;
  35         /* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */
  36         uint8_t tx_hsxv_tune;
  37         /* USB Source Impedance Adjustment. Range 0 - 0x3. */
  38         uint8_t tx_res_tune;
  39 };
  40
  41 /* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */
  42 union __packed usb3_force_gen1 {
  43                 struct {
  44                         uint8_t xhci0_port0:1;
  45                         uint8_t xhci0_port1:1;
  46                         uint8_t xhci0_port2:1;
  47                         uint8_t xhci0_port3:1;
  48                 } ports;
  49                 uint8_t usb3_port_force_gen1_en;
  50 };
  51
  52 enum rfmux_configuration_setting {
  53         USB_PD_RFMUX_SAFE_STATE = 0x0,
  54         USB_PD_RFMUX_USB31_MODE = 0x1,
  55         USB_PD_RFMUX_USB31_MODE_FLIP = 0x2,
  56         USB_PD_RFMUX_ATE_MODE = 0x3,
  57         USB_PD_RFMUX_DP_X2_MODE = 0x4,
  58         USB_PD_RFMUX_MF_MODE_ALT_D_F = 0x6,
  59         USB_PD_RFMUX_DP_X2_MODE_FLIP = 0x8,
  60         USB_PD_RFMUX_MF_MODE_ALT_D_F_FLIP = 0x9,
  61         USB_PD_RFMUX_DP_X4_MODE = 0xc,
  62 };
  63
  64 struct usb_pd_control {
  65                 uint8_t rfmux_override_en;
  66                 uint32_t rfmux_config;
  67 };
  68
  69 #define USB_PORT_COUNT  6
  70
  71 struct __packed usb3_phy_tune {
  72         uint8_t rx_eq_delta_iq_ovrd_val;
  73         uint8_t rx_eq_delta_iq_ovrd_en;
  74 };
  75 /* the RV2 USB3 port count */
  76 #define RV2_USB3_PORT_COUNT 4
  77 #define USB_PD_PORT_COUNT 2
  78
  79 enum sd_emmc_driver_strength {
  80         SD_EMMC_DRIVE_STRENGTH_B,
  81         SD_EMMC_DRIVE_STRENGTH_A,
  82         SD_EMMC_DRIVE_STRENGTH_C,
  83         SD_EMMC_DRIVE_STRENGTH_D,
  84 };
  85
  86 /* dpphy_override */
  87 enum sysinfo_dpphy_override {
  88         ENABLE_DVI_TUNINGSET = 0x01,
  89         ENABLE_HDMI_TUNINGSET = 0x02,
  90         ENABLE_HDMI6G_TUNINGSET = 0x04,
  91         ENABLE_DP_TUNINGSET = 0x08,
  92         ENABLE_DP_HBR3_TUNINGSET = 0x10,
  93         ENABLE_DP_HBR_TUNINGSET = 0x20,
  94         ENABLE_DP_HBR2_TUNINGSET = 0x40,
  95         ENABLE_EDP_TUNINGSET = 0x80,
  96 };
  97
  98 struct soc_amd_picasso_config {
  99         struct soc_amd_common_config common_config;
 100         /*
 101          * If sb_reset_i2c_peripherals() is called, this devicetree register
 102          * defines which I2C SCL will be toggled 9 times at 100 KHz.
 103          * For example, should we need I2C0 and  I2C3 have their peripheral
 104          * devices reset by toggling SCL, use:
 105          *
 106          * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
 107          */
 108         u8 i2c_scl_reset;
 109         struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
 110
 111         /* System config index */
 112         uint8_t system_config;
 113
 114         /* STAPM Configuration */
 115         uint32_t fast_ppt_limit_mW;
 116         uint32_t slow_ppt_limit_mW;
 117         uint32_t slow_ppt_time_constant_s;
 118         uint32_t stapm_time_constant_s;
 119         uint32_t sustained_power_limit_mW;
 120
 121         /* STAPM Configuration for tablet mode */
 122         uint32_t fast_ppt_limit_tablet_mode_mW;
 123         uint32_t slow_ppt_limit_tablet_mode_mW;
 124         uint32_t sustained_power_limit_tablet_mode_mW;
 125
 126         /* PROCHOT_L de-assertion Ramp Time */
 127         uint32_t prochot_l_deassertion_ramp_time_ms;
 128
 129         enum {
 130                 DOWNCORE_AUTO = 0,
 131                 DOWNCORE_1 = 1, /* Run with 1 physical core */
 132                 DOWNCORE_2 = 3, /* Run with 2 physical cores */
 133                 DOWNCORE_3 = 4, /* Run with 3 physical cores */
 134         } downcore_mode;
 135         bool smt_disable; /* true=disable SMT on all physical cores */
 136
 137         /* Lower die temperature limit */
 138         uint32_t thermctl_limit_degreeC;
 139         uint32_t thermctl_limit_tablet_mode_degreeC;
 140
 141         /* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */
 142         uint32_t psi0_current_limit_mA;
 143         uint32_t psi0_soc_current_limit_mA;
 144         uint32_t vddcr_soc_voltage_margin_mV;
 145         uint32_t vddcr_vdd_voltage_margin_mV;
 146
 147         /* VRM Limits. 0 indicates use SOC default */
 148         uint32_t vrm_maximum_current_limit_mA;
 149         uint32_t vrm_soc_maximum_current_limit_mA;
 150         uint32_t vrm_current_limit_mA;
 151         uint32_t vrm_soc_current_limit_mA;
 152
 153         /* Misc SMU settings */
 154         uint8_t sb_tsi_alert_comparator_mode_en;
 155         uint8_t core_dldo_bypass;
 156         uint8_t min_soc_vid_offset;
 157         uint8_t aclk_dpm0_freq_400MHz;
 158         uint32_t telemetry_vddcr_vdd_slope_mA;
 159         uint32_t telemetry_vddcr_vdd_offset;
 160         uint32_t telemetry_vddcr_soc_slope_mA;
 161         uint32_t telemetry_vddcr_soc_offset;
 162
 163         /*
 164          * HDMI 2.0 disable setting
 165          * bit0~3: disable HDMI 2.0 DDI0~3
 166         */
 167         uint8_t hdmi2_disable;
 168
 169         struct {
 170                 /*
 171                  * SDHCI doesn't directly support eMMC. There is an implicit mapping between
 172                  * eMMC timing modes and SDHCI UHS-I timing modes defined in the linux
 173                  * kernel.
 174                  *
 175                  *  HS    -> UHS_SDR12 (0x00)
 176                  *  DDR52 -> UHS_DDR50 (0x04)
 177                  *  HS200 -> UHS_SDR104 (0x03)
 178                  *  HS400 -> NONE (0x05)
 179                  *
 180                  * The kernel driver uses a heuristic to determine if HS400 is supported.
 181                  *
 182                  * If the eMMC MMIO device is disabled in the devicetree,
 183                  * fsps_update_emmc_config will set timing to SD_EMMC_DISABLE.
 184                 */
 185                 enum {
 186                         SD_EMMC_DISABLE,
 187                         SD_EMMC_SD_LOW_SPEED,
 188                         SD_EMMC_SD_HIGH_SPEED,
 189                         SD_EMMC_SD_UHS_I_SDR_50,
 190                         SD_EMMC_SD_UHS_I_DDR_50,
 191                         SD_EMMC_SD_UHS_I_SDR_104,
 192                         SD_EMMC_EMMC_SDR_26,
 193                         SD_EMMC_EMMC_SDR_52,
 194                         SD_EMMC_EMMC_DDR_104,
 195                         SD_EMMC_EMMC_HS200,
 196                         SD_EMMC_EMMC_HS400,
 197                         SD_EMMC_EMMC_HS300,
 198                 } timing;
 199
 200                 /*
 201                  * Sets the driver strength reflected in the SDHCI Preset Value Registers.
 202                  *
 203                  * According to the SDHCI spec:
 204                  *   The host should select the weakest drive strength that meets rise /
 205                  *   fall time requirement at system operating frequency.
 206                  */
 207                 enum sd_emmc_driver_strength sdr104_hs400_driver_strength;
 208                 enum sd_emmc_driver_strength ddr50_driver_strength;
 209                 enum sd_emmc_driver_strength sdr50_driver_strength;
 210
 211                 /*
 212                  * Sets the frequency in kHz reflected in the Initialization Preset Value
 213                  * Register.
 214                  *
 215                  * This value is used while in open-drain mode, and has a maximum value of
 216                  * 400 kHz.
 217                  */
 218                 uint16_t init_khz_preset;
 219         } emmc_config;
 220
 221         /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */
 222         union usb3_force_gen1 usb3_port_force_gen1;
 223
 224         uint8_t has_usb2_phy_tune_params;
 225         struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT];
 226         enum {
 227                 USB_OC_PIN_0    = 0x0,
 228                 USB_OC_PIN_1    = 0x1,
 229                 USB_OC_PIN_2    = 0x2,
 230                 USB_OC_PIN_3    = 0x3,
 231                 USB_OC_PIN_4    = 0x4,
 232                 USB_OC_PIN_5    = 0x5,
 233                 USB_OC_NONE     = 0xf,
 234         } usb_port_overcurrent_pin[USB_PORT_COUNT];
 235
 236         /* RV2 SOC Usb 3.1 PHY Parameters */
 237         uint8_t usb3_phy_override;
 238         /*
 239          * 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF
 240          * 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1
 241          */
 242         struct usb3_phy_tune usb3_phy_tune_params[RV2_USB3_PORT_COUNT];
 243         /* Override value for rx_vref_ctrl. Range 0 - 0x1F */
 244         uint8_t usb3_rx_vref_ctrl;
 245         /* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */
 246         uint8_t usb3_rx_vref_ctrl_en;
 247         /* Override value for tx_vboost_lvl: 0 - 0x7. */
 248         uint8_t usb_3_tx_vboost_lvl;
 249         /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */
 250         uint8_t usb_3_tx_vboost_lvl_en;
 251         /* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/
 252         uint8_t usb_3_rx_vref_ctrl_x;
 253         /* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */
 254         uint8_t usb_3_rx_vref_ctrl_en_x;
 255         /* Override value for tx_vboost_lvl: 0 - 0x7. */
 256         uint8_t usb_3_tx_vboost_lvl_x;
 257         /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */
 258         uint8_t usb_3_tx_vboost_lvl_en_x;
 259
 260         /* The array index is the general purpose PCIe clock output number. Values in here
 261            aren't the values written to the register to have the default to be always on. */
 262         enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
 263
 264         /* performance policy for the PCIe links: power consumption vs. link speed */
 265         enum {
 266                 DXIO_PSPP_DISABLED = 0,
 267                 DXIO_PSPP_PERFORMANCE,
 268                 DXIO_PSPP_BALANCED,
 269                 DXIO_PSPP_POWERSAVE,
 270         } pspp_policy;
 271
 272         /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
 273         bool acp_i2s_use_external_48mhz_osc;
 274
 275         /* eDP phy tuning settings */
 276         uint16_t edp_phy_override;
 277         /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */
 278         uint8_t edp_physel;
 279
 280         struct {
 281                 uint8_t dp_vs_pemph_level;
 282                 uint8_t deemph_6db4;
 283                 uint8_t boostadj;
 284                 uint16_t margin_deemph;
 285         } edp_tuningset;
 286
 287         /*
 288          * eDP panel power sequence control
 289          * all pwr sequence numbers below are in uint of 4ms and "0" as default value
 290          */
 291         uint8_t edp_pwr_adjust_enable;
 292         uint8_t pwron_digon_to_de;
 293         uint8_t pwron_de_to_varybl;
 294         uint8_t pwrdown_varybloff_to_de;
 295         uint8_t pwrdown_de_to_digoff;
 296         uint8_t pwroff_delay;
 297         uint8_t pwron_varybl_to_blon;
 298         uint8_t pwrdown_bloff_to_varybloff;
 299         uint8_t min_allowed_bl_level;
 300
 301         /* allow USB PD port setting override */
 302         struct usb_pd_control usb_pd_config_override[USB_PD_PORT_COUNT];
 303 };
 304
 305 #endif /* __PICASSO_CHIP_H__ */