src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/alib.h>
   4 #include <arch/vga.h>
   5
   6 External(\_SB.ALIB, MethodObj)
   7
   8 /* System Bus */
   9 /*  _SB.PCI0 */
  10
  11 /* Describe the Southbridge devices */
  12
  13 /* 0:14.0 - SMBUS */
  14 Device(SBUS) {
  15         Name(_ADR, 0x00140000)
  16 } /* end SBUS */
  17
  18 #include "usb.asl"
  19
  20 /* 0:14.2 - I2S Audio */
  21
  22 /* 0:14.3 - LPC */
  23 #include <soc/amd/common/acpi/lpc.asl>
  24
  25 /* 0:14.7 - SD Controller */
  26 Device(SDCN) {
  27         Name(_ADR, 0x00140007)
  28
  29         Method(_PS0) {
  30                 FDDC(24, 0)
  31         }
  32         Method(_PS3) {
  33                 FDDC(24, 3)
  34         }
  35         Method(_PSC) {
  36                 Return(SDTD)
  37         }
  38 } /* end SDCN */
  39
  40 Name(CRES, ResourceTemplate() {
  41         /* Set the Bus number and Secondary Bus number for the PCI0 device
  42          * The Secondary bus range for PCI0 lets the system
  43          * know what bus values are allowed on the downstream
  44          * side of this PCI bus if there is a PCI-PCI bridge.
  45          * PCI buses can have 256 secondary buses which
  46          * range from [0-0xFF] but they do not need to be
  47          * sequential.
  48          */
  49         WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
  50                 0x0000,         /* address granularity */
  51                 0x0000,         /* range minimum */
  52                 0x00ff,         /* range maximum */
  53                 0x0000,         /* translation */
  54                 0x0100,         /* length */
  55                 ,, PSB0)                /* ResourceSourceIndex, ResourceSource, DescriptorName */
  56
  57         IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
  58
  59         WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
  60                 0x0000,         /* address granularity */
  61                 0x0000,         /* range minimum */
  62                 0x0cf7,         /* range maximum */
  63                 0x0000,         /* translation */
  64                 0x0cf8          /* length */
  65         )
  66
  67         WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
  68                 0x0000,         /* address granularity */
  69                 0x0d00,         /* range minimum */
  70                 0xffff,         /* range maximum */
  71                 0x0000,         /* translation */
  72                 0xf300          /* length */
  73         )
  74
  75         Memory32Fixed(READONLY, VGA_MMIO_BASE, VGA_MMIO_SIZE, VGAM)     /* VGA memory space */
  76         Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1)   /* Assume C0000-E0000 empty */
  77
  78         /* memory space for PCI BARs below 4GB */
  79         Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
  80 }) /* End Name(_SB.PCI0.CRES) */
  81
  82 Method(_CRS, 0) {
  83         /* DBGO("\\_SB\\PCI0\\_CRS\n") */
  84         CreateDWordField(CRES, ^MMIO._BAS, MM1B)
  85         CreateDWordField(CRES, ^MMIO._LEN, MM1L)
  86
  87         /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
  88         MM1B = TOM1
  89         Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
  90         Local0 -= TOM1
  91         MM1L = Local0
  92
  93         CreateWordField(CRES, ^PSB0._MAX, BMAX)
  94         CreateWordField(CRES, ^PSB0._LEN, BLEN)
  95         BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
  96         BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
  97
  98         Return (CRES) /* note to change the Name buffer */
  99 } /* end of Method(_SB.PCI0._CRS) */
 100
 101 /*
 102  *
 103  *               FIRST METHOD CALLED UPON BOOT
 104  *
 105  *  1. If debugging, print current OS and ACPI interpreter.
 106  *  2. Get PCI Interrupt routing from ACPI VSM, this
 107  *     value is based on user choice in BIOS setup.
 108  */
 109 Method(_INI, 0, Serialized) {
 110         /* DBGO("\\_SB\\_INI\n") */
 111         /* DBGO("   DSDT.ASL code from ") */
 112         /* DBGO(__DATE__) */
 113         /* DBGO(" ") */
 114         /* DBGO(__TIME__) */
 115         /* DBGO("\n   Sleep states supported: ") */
 116         /* DBGO("\n") */
 117         /* DBGO("   \\_OS=") */
 118         /* DBGO(\_OS) */
 119         /* DBGO("\n   \\_REV=") */
 120         /* DBGO(\_REV) */
 121         /* DBGO("\n") */
 122
 123         /* Send ALIB Function 1 the AC/DC state */
 124         Name(F1BF, Buffer(0x03){})
 125         CreateWordField(F1BF, 0, F1SZ)
 126         CreateByteField(F1BF, 2, F1DA)
 127
 128         F1SZ = 3
 129         F1DA= \PWRS
 130
 131         \_SB.ALIB(ALIB_FUNCTION_REPORT_AC_DC_STATE, F1BF)
 132
 133 } /* End Method(_SB._INI) */
 134
 135 OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000)
 136 Field( SMIC, ByteAcc, NoLock, Preserve) {
 137         /* MISC registers */
 138         offset (0x03ee),
 139         U3PS, 2,  /* Usb3PowerSel */
 140
 141         offset (0x0e28),
 142         ,29 ,
 143         SARP, 1,  /* Sata Ref Clock Powerdown */
 144         U2RP, 1,  /* Usb2 Ref Clock Powerdown */
 145         U3RP, 1,  /* Usb3 Ref Clock Powerdown */
 146
 147         /* XHCI_PM registers */
 148         offset (0x1c00),
 149         , 1,
 150         ,6,
 151         U3PY, 1,
 152         , 7,
 153         UD3P, 1,  /* bit 15 */
 154         U3PR, 1,  /* bit 16 */
 155         , 11,
 156         FWLM, 1,  /* FirmWare Load Mode  */
 157         FPLS, 1,  /* Fw PreLoad Start    */
 158         FPLC, 1,  /* Fw PreLoad Complete */
 159
 160         offset (0x1c04),
 161         UA04, 16,
 162         , 15,
 163         ROAM, 1,  /* 1= ROM 0=RAM */
 164
 165         offset (0x1c08),
 166         UA08, 32,
 167
 168         /* AOAC Registers */
 169         offset (0x1e4a), /* I2C0 D3 Control */
 170         I0TD, 2,
 171         , 1,
 172         I0PD, 1,
 173         offset (0x1e4b), /* I2C0 D3 State */
 174         I0DS, 3,
 175
 176         offset (0x1e4c), /* I2C1 D3 Control */
 177         I1TD, 2,
 178         , 1,
 179         I1PD, 1,
 180         offset (0x1e4d), /* I2C1 D3 State */
 181         I1DS, 3,
 182
 183         offset (0x1e4e), /* I2C2 D3 Control */
 184         I2TD, 2,
 185         , 1,
 186         I2PD, 1,
 187         offset (0x1e4f), /* I2C2 D3 State */
 188         I2DS, 3,
 189
 190         offset (0x1e50), /* I2C3 D3 Control */
 191         I3TD, 2,
 192         , 1,
 193         I3PD, 1,
 194         offset (0x1e51), /* I2C3 D3 State */
 195         I3DS, 3,
 196
 197         offset (0x1e56), /* UART0 D3 Control */
 198         U0TD, 2,
 199         , 1,
 200         U0PD, 1,
 201         offset (0x1e57), /* UART0 D3 State */
 202         U0DS, 3,
 203
 204         offset (0x1e58), /* UART1 D3 Control */
 205         U1TD, 2,
 206         , 1,
 207         U1PD, 1,
 208         offset (0x1e59), /* UART1 D3 State */
 209         U1DS, 3,
 210
 211         offset (0x1e5e), /* SATA D3 Control */
 212         SATD, 2,
 213         , 1,
 214         SAPD, 1,
 215         offset (0x1e5f), /* SATA D3 State */
 216         SADS, 3,
 217
 218         offset (0x1e64), /* USB2 D3 Control */
 219         U2TD, 2,
 220         , 1,
 221         U2PD, 1,
 222         offset (0x1e65), /* USB2 D3 State */
 223         U2DS, 3,
 224
 225         offset (0x1e6e), /* USB3 D3 Control */
 226         U3TD, 2,
 227         , 1,
 228         U3PD, 1,
 229         offset (0x1e6f), /* USB3 D3 State */
 230         U3DS, 3,
 231
 232         offset (0x1e70), /* SD D3 Control */
 233         SDTD, 2,
 234         , 1,
 235         SDPD, 1,
 236         , 1,
 237         , 1,
 238         SDRT, 1,
 239         SDSC, 1,
 240
 241         offset (0x1e71), /* SD D3 State */
 242         SDDS, 3,
 243
 244         offset (0x1e80), /* Shadow Register Request */
 245         , 15,
 246         RQ15, 1,
 247         , 2,
 248         RQ18, 1,
 249         , 4,
 250         RQ23, 1,
 251         RQ24, 1,
 252         , 5,
 253         RQTY, 1,
 254         offset (0x1e84), /* Shadow Register Status */
 255         , 15,
 256         SASR, 1,  /* SATA 15 Shadow Reg Request Status Register */
 257         , 2,
 258         U2SR, 1,  /* USB2 18 Shadow Reg Request Status Register */
 259         , 4,
 260         U3SR, 1,  /* USB3 23 Shadow Reg Request Status Register */
 261         SDSR, 1,  /* SD 24 Shadow Reg Request Status Register */
 262
 263         offset (0x1ea0), /* PwrGood Control */
 264         PG1A, 1,
 265         PG2_, 1,
 266         ,1,
 267         U3PG, 1,  /* Usb3 Power Good BIT3 */
 268
 269         offset (0x1ea3), /* PwrGood Control b[31:24] */
 270         PGA3, 8 ,
 271 }
 272
 273 Field(PCFG, DwordAcc, NoLock, Preserve)
 274 {
 275         /* XHCI */
 276         Offset(0x00080010), /* Base address */
 277         XHBA, 32,
 278         Offset(0x0008002c), /* Subsystem ID / Vendor ID */
 279         XH2C, 32,
 280
 281         Offset(0x00080048), /* Indirect PCI Index Register */
 282         IDEX, 32,
 283         DATA, 32,
 284         Offset(0x00080054), /* PME Control / Status */
 285         U_PS, 2,
 286
 287         /* EHCI */
 288         Offset(0x00090004), /* Control */
 289         , 1,
 290         EHME, 1,
 291         Offset(0x00090010), /* Base address */
 292         EHBA, 32,
 293         Offset(0x0009002c), /* Subsystem ID / Vendor ID */
 294         EH2C, 32,
 295         Offset(0x00090054), /* EHCI Spare 1 */
 296         EH54, 8,
 297         Offset(0x00090064), /* Misc Control 2 */
 298         EH64, 8,
 299
 300         Offset(0x000900c4), /* PME Control / Status */
 301         E_PS, 2,
 302
 303         /* LPC Bridge */
 304         Offset(0x000a30cb), /* ClientRomProtect[31:24] */
 305         ,  7,
 306         AUSS,  1, /* AutoSizeStart */
 307 }
 308
 309 /*
 310  * Arg0:device:
 311  *  5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1,
 312  *  15=SATA, 18=EHCI, 23=xHCI, 24=SD
 313  * Arg1:D-state
 314  */
 315 Mutex (FDAS, 0) /* FCH Device AOAC Semophore */
 316 Method(FDDC, 2, Serialized)
 317 {
 318         Acquire(FDAS, 0xffff)
 319
 320         if (Arg1 == 0) {
 321                 Switch(ToInteger(Arg0)) {
 322                         Case(Package() {5, 15, 24}) {
 323                                 PG1A = 1
 324                         }
 325                         Case(Package() {6, 7, 8, 11, 12, 18}) {
 326                                 PG2_ = 1
 327                         }
 328                 }
 329                 /* put device into D0 */
 330                 Switch(ToInteger(Arg0))
 331                 {
 332                         Case(5) {
 333                                 I0TD = 0x00
 334                                 I0PD = 1
 335                                 Local0 = I0DS
 336                                 while(Local0 != 0x7) {
 337                                         Local0 = I0DS
 338                                 }
 339                         }
 340                         Case(6) {
 341                                 I1TD = 0x00
 342                                 I1PD = 1
 343                                 Local0 = I1DS
 344                                 while(Local0 != 0x7) {
 345                                         Local0 = I1DS
 346                                 }
 347                         }
 348                         Case(7) {
 349                                 I2TD = 0x00
 350                                 I2PD = 1
 351                                 Local0 = I2DS
 352                                 while(Local0 != 0x7) {
 353                                         Local0 = I2DS
 354                                 }
 355                         }
 356                         Case(8) {
 357                                 I3TD = 0x00
 358                                 I3PD = 1
 359                                 Local0 = I3DS
 360                                 while(Local0 != 0x7) {
 361                                         Local0 = I3DS
 362                                 }
 363                         }
 364                         Case(11) {
 365                                 U0TD = 0x00
 366                                 U0PD = 1
 367                                 Local0 = U0DS
 368                                 while(Local0 != 0x7) {
 369                                         Local0 = U0DS
 370                                 }
 371                         }
 372                         Case(12) {
 373                                 U1TD = 0x00
 374                                 U1PD = 1
 375                                 Local0 = U1DS
 376                                 while(Local0 != 0x7) {
 377                                         Local0 = U1DS
 378                                 }
 379                         }
 380 /* todo                 Case(15) { STD0()} */ /* SATA */
 381                         Case(18) { U2D0()} /* EHCI */
 382                         Case(23) { U3D0()} /* XHCI */
 383                         Case(24) { /* SD */
 384                                 SDTD = 0x00
 385                                 SDPD = 1
 386                                 Local0 = SDDS
 387                                 while(Local0 != 0x7) {
 388                                         Local0 = SDDS
 389                                 }
 390                         }
 391                 }
 392         } else {
 393                 /* put device into D3cold */
 394                 Switch(ToInteger(Arg0))
 395                 {
 396                         Case(5) {
 397                                 I0PD = 0
 398                                 Local0 = I0DS
 399                                 while(Local0 != 0x0) {
 400                                         Local0 = I0DS
 401                                 }
 402                                 I0TD = 0x03
 403                         }
 404                         Case(6) {
 405                                 I1PD = 0
 406                                 Local0 = I1DS
 407                                 while(Local0 != 0x0) {
 408                                         Local0 = I1DS
 409                                 }
 410                                 I1TD = 0x03
 411                         }
 412                         Case(7) {
 413                                 I2PD = 0
 414                                 Local0 = I2DS
 415                                 while(Local0 != 0x0) {
 416                                         Local0 = I2DS
 417                                 }
 418                                 I2TD = 0x03
 419                         }
 420                         Case(8) {
 421                                 I3PD = 0
 422                                 Local0 = I3DS
 423                                 while(Local0 != 0x0) {
 424                                         Local0 = I3DS
 425                                 }
 426                                 I3TD = 0x03
 427                         }
 428                         Case(11) {
 429                                 U0PD = 0
 430                                 Local0 = U0DS
 431                                 while(Local0 != 0x0) {
 432                                         Local0 = U0DS
 433                                 }
 434                                 U0TD = 0x03
 435                         }
 436                         Case(12) {
 437                                 U1PD = 0
 438                                 Local0 = U1DS
 439                                 while(Local0 != 0x0) {
 440                                         Local0 = U1DS
 441                                 }
 442                                 U1TD = 0x03
 443                         }
 444 /* todo                 Case(15) { STD3()} */ /* SATA */
 445                         Case(18) { U2D3()} /* EHCI */
 446                         Case(23) { U3D3()} /* XHCI */
 447                         Case(24) { /* SD */
 448                                 SDPD = 0
 449                                 Local0 = SDDS
 450                                 while(Local0 != 0x0) {
 451                                         Local0 = SDDS
 452                                 }
 453                                 SDTD = 0x03
 454                         }
 455                 }
 456                 /* Turn off Power */
 457                 if (I0TD == 3) {
 458                         if (SATD == 3) {
 459                                 if (SDTD == 3) { PG1A = 0 }
 460                         }
 461                 }
 462                 if (I1TD == 3) {
 463                         if (I2TD == 3) {
 464                                 if (I3TD == 3) {
 465                                         if (U0TD == 3) {
 466                                                 if (U1TD == 3) {
 467                                                         if (U2TD == 3) {
 468                                                                 PG2_ = 0
 469                                                         }
 470                                                 }
 471                                         }
 472                                 }
 473                         }
 474                 }
 475         }
 476         Release(FDAS)
 477 }
 478
 479 Method(FPTS,0, Serialized)  /* FCH _PTS */
 480 {
 481         if (\XHCE == one) {
 482                 if (U3TD != 0x03) {
 483                         FDDC(23, 3)
 484                 }
 485         }
 486         if (U2TD != 0x03) {
 487                 FDDC(18, 3)
 488         }
 489 }
 490
 491 Method(FWAK,0, Serialized)  /* FCH _WAK */
 492 {
 493         if (\XHCE == one) {
 494                 if (U3TD == 0x03) {
 495                         FDDC(23, 0)
 496                 }
 497         }
 498         if (U2TD == 0x03) {
 499                 FDDC(18, 0)
 500         }
 501         if (\UT0E == zero) {
 502                 if (U0TD != 0x03) {
 503                         FDDC(11, 3)
 504                 }
 505         }
 506         if (\UT1E == zero) {
 507                 if (U1TD != 0x03) {
 508                         FDDC(12, 3)
 509                 }
 510         }
 511         if (\IC0E == zero) {
 512                 if (I0TD != 0x03) {
 513                         FDDC(5, 3)
 514                 }
 515         }
 516         if (\IC1E == zero) {
 517                 if (I1TD != 0x03) {
 518                         FDDC(6, 3)
 519                 }
 520         }
 521         if (\IC2E == zero) {
 522                 if (I2TD != 0x03) {
 523                         FDDC(7, 3)
 524                 }
 525         }
 526         if (\IC3E == zero) {
 527                 if (I3TD != 0x03) {
 528                         FDDC(8, 3)
 529                 }
 530         }
 531 }
 532
 533 /*
 534  * Helper for setting a bit in AOACxA0 PwrGood Control
 535  * Arg0: bit to set or clear
 536  * Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0]
 537  */
 538 Method(PWGC,2, Serialized)
 539 {
 540         Local0 = PGA3 & 0xdf  /* do SwUsb3SlpShutdown below */
 541         if (Arg1) {
 542                 Local0 |= Arg0
 543         } else {
 544                 Local1 = ~Arg0
 545                 Local0 &= Local1
 546         }
 547         PGA3 = Local0
 548         if (Arg0 == 0x20) { /* if SwUsb3SlpShutdown */
 549                 Local0 = PGA3
 550                 Local0 &= Arg0
 551                 while(!Local0) { /* wait SwUsb3SlpShutdown to complete */
 552                         Local0 = PGA3
 553                         Local0 &= Arg0
 554                 }
 555         }
 556 }