src/soc/amd/stoneyridge/tsc_freq.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <amdblocks/cpu.h>
   4 #include <cpu/x86/msr.h>
   5 #include <cpu/amd/msr.h>
   6 #include <cpu/x86/tsc.h>
   7 #include <console/console.h>
   8 #include <soc/pci_devs.h>
   9 #include <soc/msr.h>
  10 #include <device/pci_ops.h>
  11
  12 unsigned long tsc_freq_mhz(void)
  13 {
  14         union pstate_msr pstate_reg;
  15
  16         /*
  17          * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for
  18          * MSR0000_0010.  The TSC increments at the P0 frequency. According
  19          * to the "Software P-state Numbering" section, P0 is the highest
  20          * non-boosted state.  freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
  21          */
  22         pstate_reg.raw = rdmsr(PSTATE_MSR(get_pstate_0_reg())).raw;
  23         if (!pstate_reg.pstate_en)
  24                 die("Unknown error: cannot determine P-state 0\n");
  25
  26         return get_pstate_core_freq(pstate_reg);
  27 }