src/soc/intel/xeon_sp/skx/soc_util.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <assert.h>
   4 #include <console/console.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <hob_iiouds.h>
   8 #include <intelblocks/cpulib.h>
   9 #include <intelblocks/pcr.h>
  10 #include <soc/iomap.h>
  11 #include <soc/msr.h>
  12 #include <soc/pci_devs.h>
  13 #include <soc/pcr_ids.h>
  14 #include <soc/soc_util.h>
  15 #include <soc/util.h>
  16
  17
  18 /*
  19  *     +-------------------------+  TOLM
  20  *     | System Management Mode  |
  21  *     |      code and data      |
  22  *     |         (TSEG)          |
  23  *     +-------------------------+  SMM base (aligned)
  24  *     |                         |
  25  *     | Chipset Reserved Memory |
  26  *     |                         |
  27  *     +-------------------------+  top_of_ram (aligned)
  28  *     |                         |
  29  *     |       CBMEM Root        |
  30  *     |                         |
  31  *     +-------------------------+
  32  *     |                         |
  33  *     |   FSP Reserved Memory   |
  34  *     |                         |
  35  *     +-------------------------+
  36  *     |                         |
  37  *     |  Various CBMEM Entries  |
  38  *     |                         |
  39  *     +-------------------------+  top_of_stack (8 byte aligned)
  40  *     |                         |
  41  *     |   stack (CBMEM Entry)   |
  42  *     |                         |
  43  *     +-------------------------+
  44  */
  45
  46 const struct SystemMemoryMapHob *get_system_memory_map(void)
  47 {
  48         size_t hob_size;
  49         const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
  50         const struct SystemMemoryMapHob *memmap_addr;
  51
  52         memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
  53         assert(memmap_addr && hob_size != 0);
  54
  55         return memmap_addr;
  56 }
  57
  58 bool is_pcie_iio_stack_res(const STACK_RES *res)
  59 {
  60         return res->BusBase < res->BusLimit;
  61 }
  62
  63 bool is_ubox_stack_res(const STACK_RES *res)
  64 {
  65         /*
  66          * Unlike on later platforms there's no separate "UBOX" stack.
  67          *
  68          * The UBOX devices can always be found on the first bus on the stack IIO0 (CSTACK).
  69          * This bus is also referred to as uncore bus 0 or B(30).
  70          * It has at a fixed address the UBOX:
  71          * B(30):8.0 8086:2014
  72          * B(30):8.1 8086:2015
  73          * B(30):8.2 8086:2016
  74          *
  75          * The PCU devices can always be on the first bus of the stack IIO1 (PSTACK).
  76          * This bus is also referred to as uncore bus 1 or B(31).
  77          * It has at a fixed address the PCU:
  78          * B(31):30.0 8086:2080
  79          * B(31):30.1 8086:2081
  80          * B(31):30.2 8086:2082
  81          */
  82
  83         return false;
  84 }
  85
  86 #if ENV_RAMSTAGE
  87 void config_reset_cpl3_csrs(void)
  88 {
  89         uint32_t data;
  90         struct device *dev;
  91
  92         // FIXME: Looks like this needs to run after FSP-S since it modifies FSP defaults!
  93
  94         dev = NULL;
  95         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) {
  96                 data = pci_read_config32(dev, PCU_CR1_SAPMCTL);
  97                 /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
  98                 data &= 0x0fffffff;
  99                 pci_write_config32(dev, PCU_CR1_SAPMCTL, data);
 100         }
 101
 102         dev = NULL;
 103         while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
 104                 data = PCIE_IN_PKGCSTATE_L1_MASK;
 105                 pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
 106
 107                 data = KTI_IN_PKGCSTATE_L1_MASK;
 108                 pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
 109
 110                 data = PROCHOT_RATIO;
 111                 printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
 112                 pci_write_config32(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
 113                 dump_csr(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
 114
 115                 data = pci_read_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
 116                 data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
 117                 pci_write_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
 118         }
 119 }
 120 #endif
 121
 122 /*
 123  * EX: SKX-SP
 124  * Ports    Stack   Stack(HOB)  IioConfigIou
 125  * ==========================================
 126  * 0        CSTACK      stack 0     IOU0
 127  * 1A..1D   PSTACKZ     stack 1     IOU1
 128  * 2A..2D   PSTACK1     stack 2     IOU2
 129  * 3A..3D   PSTACK2     stack 3     IOU3
 130  * 5A..4D   PSTACK3     stack 4     IOU4
 131  * 5A..5D   PSTACK4     stack 5     IOU5
 132  */
 133 int soc_get_stack_for_port(int port)
 134 {
 135         if (port == PORT_0)
 136                 return CSTACK;
 137         else if (port >= PORT_1A && port <= PORT_1D)
 138                 return PSTACK0;
 139         else if (port >= PORT_2A && port <= PORT_2D)
 140                 return PSTACK1;
 141         else if (port >= PORT_3A && port <= PORT_3D)
 142                 return PSTACK2;
 143         else if (port >= PORT_4A && port <= PORT_4D)
 144                 return PSTACK3; // MCP0
 145         else if (port >= PORT_5A && port <= PORT_5D)
 146                 return PSTACK4; // MCP1
 147         else
 148                 return -1;
 149 }
 150
 151 uint8_t soc_get_iio_ioapicid(int socket, int stack)
 152 {
 153         uint8_t ioapic_id = socket ? 0xf : 0x9;
 154         switch (stack) {
 155         case CSTACK:
 156                 break;
 157         case PSTACK0:
 158                 ioapic_id += 1;
 159                 break;
 160         case PSTACK1:
 161                 ioapic_id += 2;
 162                 break;
 163         case PSTACK2:
 164                 ioapic_id += 3;
 165                 break;
 166         default:
 167                 return 0xff;
 168         }
 169         return ioapic_id;
 170 }
 171
 172 bool is_memtype_reserved(uint16_t mem_type)
 173 {
 174         return !!(mem_type & MEM_TYPE_RESERVED);
 175 }
 176
 177 bool is_memtype_non_volatile(uint16_t mem_type)
 178 {
 179         return !(mem_type & MEMTYPE_VOLATILE_MASK);
 180 }
 181
 182 bool is_memtype_processor_attached(uint16_t mem_type)
 183 {
 184         return true;
 185 }
 186
 187 uint8_t get_cxl_node_count(void)
 188 {
 189         return 0;
 190 }
 191
 192 bool get_mmio_high_base_size(resource_t *base, resource_t *size)
 193 {
 194         return false;
 195 }