acpi_gic: Add helper for platform gicc
[coreboot2.git] / src / mainboard / google / butterfly / devicetree.cb
blobcb34f3c55edd70029bd725ae1619bee666628654
1 chip northbridge/intel/sandybridge
2 # IGD Displays
3 register "gfx" = "GMA_STATIC_DISPLAYS(0)"
5 # Enable DisplayPort Hotplug with 6ms pulse
6 register "gpu_dp_d_hotplug" = "0x06"
9 # Enable Panel as LVDS and configure power delays
10 register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
11 register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
12 register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
13 register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
14 register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
15 register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
17 # Set backlight PWM values
18 register "gpu_cpu_backlight" = "0x000001e8"
19 register "gpu_pch_backlight" = "0x03d00000"
21 register "spd_addresses" = "{0x50, 0, 0x52, 0}"
22 register "ec_present" = "1"
23 # FIXME: Native raminit requires reduced max clock
24 register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
25 # Force double refresh rate
26 register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE"
28 device domain 0 on
29 device ref host_bridge on end # host bridge
30 device ref peg10 off end # PCIe Bridge for discrete graphics
31 device ref igd on end # vga controller
33 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
34 # GPI routing
35 # 0 No effect (default)
36 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
37 # 2 SCI (if corresponding GPIO_EN bit is also set)
38 register "alt_gp_smi_en" = "0x0000"
39 #register "gpi1_routing" = "1" #SMI from EC
40 register "gpi13_routing" = "2" #SCI from EC
42 # Enable SATA ports 0 & 1
43 register "sata_port_map" = "0x3"
44 # Set max SATA speed to 3.0 Gb/s
45 register "sata_interface_speed_support" = "0x2"
47 # Enable EC Port 0x68/0x6C
48 register "gen1_dec" = "0x00040069"
50 # EC range is 0x380-0387
51 register "gen2_dec" = "0x00040381"
53 # Enable zero-based linear PCIe root port functions
54 register "pcie_port_coalesce" = "true"
56 register "usb_port_config" = "{
57 {1, 0, -1}, /* P0: Right USB 3.0 #1 (no OC) */
58 {1, 0, -1}, /* P1: Right USB 3.0 #2 (no OC) */
59 {1, 0, -1}, /* P2: Camera (no OC) */
60 /* P3-P8: Empty */
61 {0, 0, -1}, {0, 0, -1}, {0, 0, -1},
62 {0, 0, -1}, {0, 0, -1}, {0, 0, -1},
63 {1, 1, -1}, /* P9: Left USB 1 (no OC) */
64 {1, 0, -1}, /* P10: Mini PCIe - WLAN / BT (no OC) */
65 /* P11-P13: Empty */
66 {0, 0, -1}, {0, 0, -1}, {0, 0, -1}
69 device ref xhci on end # USB 3.0 Controller
70 device ref mei1 on end # Management Engine Interface 1
71 device ref mei2 off end # Management Engine Interface 2
72 device ref me_ide_r off end # Management Engine IDE-R
73 device ref me_kt off end # Management Engine KT
74 device ref gbe off end # Intel Gigabit Ethernet
75 device ref ehci2 on end # USB2 EHCI #2
76 device ref hda on end # High Definition Audio
77 device ref pcie_rp1 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug)
78 device ref pcie_rp2 on end # PCIe Port #2 (ETH0)
79 device ref pcie_rp3 on end # PCIe Port #3 (Card Reader)
80 #force ASPM for PCIe bridge to Card Reader
81 register "pcie_aspm[2]" = "0x3"
82 device ref pcie_rp4 off end # PCIe Port #4
83 device ref pcie_rp5 off end # PCIe Port #5
84 device ref pcie_rp6 off end # PCIe Port #6
85 device ref pcie_rp7 off end # PCIe Port #7
86 device ref pcie_rp8 off end # PCIe Port #8
87 device ref ehci1 on end # USB2 EHCI #1
88 device ref pci_bridge off end # PCI bridge
89 device ref lpc on #LPC bridge
90 chip drivers/pc80/tpm
91 device pnp 0c31.0 on end
92 end
93 chip ec/quanta/ene_kb3940q
94 # 60/64 KBC
95 device pnp ff.1 on # dummy address
96 end
97 end
98 end # LPC bridge
99 device ref sata1 on end # SATA Controller 1
100 device ref smbus on
101 subsystemid 0x18D1 0x04B4
102 end # SMBus
103 device ref sata2 off end # SATA Controller 2
104 device ref thermal on end # Thermal