src/include/device/dram/ddr2.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /*
   4  * JEDEC Standard No. 21-C
   5  * Annex J: Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)
   6  */
   7
   8 #ifndef DEVICE_DRAM_DDR2L_H
   9 #define DEVICE_DRAM_DDR2L_H
  10
  11 /**
  12  * @file ddr2.h
  13  *
  14  * \brief Utilities for decoding DDR2 SPDs
  15  */
  16
  17 #include <stdint.h>
  18 #include <spd.h>
  19 #include <device/dram/common.h>
  20 #include <stdbool.h>
  21
  22 /** Maximum SPD size supported */
  23 #define SPD_SIZE_MAX_DDR2       128
  24
  25 /* Byte 20 [5:0]: DDR2 Module type information */
  26 enum spd_dimm_type_ddr2 {
  27         SPD_DDR2_DIMM_TYPE_UNDEFINED            = 0x00,
  28         SPD_DDR2_DIMM_TYPE_RDIMM                = 0x01,
  29         SPD_DDR2_DIMM_TYPE_UDIMM                = 0x02,
  30         SPD_DDR2_DIMM_TYPE_SO_DIMM              = 0x04,
  31         SPD_DDR2_DIMM_TYPE_72B_SO_CDIMM         = 0x06,
  32         SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM         = 0x07,
  33         SPD_DDR2_DIMM_TYPE_MICRO_DIMM           = 0x08,
  34         SPD_DDR2_DIMM_TYPE_MINI_RDIMM           = 0x10,
  35         SPD_DDR2_DIMM_TYPE_MINI_UDIMM           = 0x20,
  36         /* Masks to bits 5:0 to give the dimm type */
  37         SPD_DDR2_DIMM_TYPE_MASK                 = 0x3f,
  38 };
  39
  40 /**
  41  * \brief DIMM flags
  42  *
  43  * Characteristic flags for the DIMM, as presented by the SPD
  44  */
  45 union dimm_flags_ddr2_st {
  46         /* The whole point of the union/struct construct is to allow us to clear
  47          * all the bits with one line: flags.raw = 0.
  48          * We do not care how these bits are ordered */
  49         struct {
  50                 /* Module can work at 5.00V */
  51                 unsigned int operable_5_00V:1;
  52                 /* Module can work at 3.33V */
  53                 unsigned int operable_3_33V:1;
  54                 /* Module can work at 2.50V */
  55                 unsigned int operable_2_50V:1;
  56                 /* Module can work at 1.80V - All DIMMS must be 1.8V operable */
  57                 unsigned int operable_1_80V:1;
  58                 /* Module can work at 1.50V */
  59                 unsigned int operable_1_50V:1;
  60                 /* Module can work at 1.35V */
  61                 unsigned int operable_1_35V:1;
  62                 /* Module can work at 1.20V */
  63                 unsigned int operable_1_25V:1;
  64                 /* Has an 8-bit bus extension, meaning the DIMM supports ECC */
  65                 unsigned int is_ecc:1;
  66                 /* Supports weak driver */
  67                 unsigned int weak_driver:1;
  68                 /* Supports terminating at 50 Ohm */
  69                 unsigned int terminate_50ohms:1;
  70                 /* Partial Array Self Refresh */
  71                 unsigned int pasr:1;
  72                 /* Supports burst length 8 */
  73                 unsigned int bl8:1;
  74                 /* Supports burst length 4 */
  75                 unsigned int bl4:1;
  76                 /* DIMM Package is stack */
  77                 unsigned int stacked:1;
  78                 /* the assembly supports self refresh */
  79                 unsigned int self_refresh:1;
  80         };
  81         unsigned int raw;
  82 };
  83
  84 /**
  85  * \brief DIMM characteristics
  86  *
  87  * The characteristics of each DIMM, as presented by the SPD
  88  */
  89 struct dimm_attr_ddr2_st {
  90         enum spd_memory_type dram_type;
  91         enum spd_dimm_type_ddr2 dimm_type;
  92         /* BCD SPD revision */
  93         u8 rev;
  94         /* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */
  95         u8 cas_supported;
  96         /* Maximum clock to data cycle times for various CAS.
  97          * Fields 0 and 1 are unused. */
  98         u32 cycle_time[8];
  99         /* Maximum data access times for various CAS.
 100          * Fields 0 and 1 are unused. */
 101         u32 access_time[8];
 102         /* Flags extracted from SPD */
 103         union dimm_flags_ddr2_st flags;
 104         /* Number of banks */
 105         u8 banks;
 106         /* SDRAM width */
 107         u8 width;
 108         /* Module width */
 109         u8 mod_width;
 110         /* Number of ranks */
 111         u8 ranks;
 112         /* Number or row address bits */
 113         u8 row_bits;
 114         /* Number or column address bits */
 115         u8 col_bits;
 116         /* Number of PLLs on module */
 117         u8 plls;
 118         /* Size of module in MiB */
 119         u16 size_mb;
 120         /* Size of one rank in MiB */
 121         u16 ranksize_mb;
 122         /* Latencies are in units of 1/256 ns */
 123         u32 tCK;
 124         u32 tWR;
 125         u32 tRCD;
 126         u32 tRRD;
 127         u32 tRP;
 128         u32 tRAS;
 129         u32 tIS;
 130         u32 tIH;
 131         u32 tDS;
 132         u32 tDH;
 133
 134         u32 tRC;
 135         u32 tRFC;
 136         u32 tWTR;
 137         u32 tRTP;
 138         u32 tDQSQ;
 139         u32 tQHS;
 140
 141         /* Latencies are in units of 1/256 us */
 142         u32 tPLL;
 143         u32 tRR;
 144
 145         u8 checksum;
 146         /* Manufacturer ID */
 147         u32 manufacturer_id;
 148         /* ASCII part number - NULL terminated */
 149         u8 part_number[17];
 150         /* Year manufactured */
 151         u16 year;
 152         /* Week manufactured */
 153         u8 weeks;
 154         /* Unique serial number */
 155         u32 serial;
 156 };
 157
 158 bool spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type);
 159 u8 spd_ddr2_calc_checksum(u8 *spd, int len);
 160 u32 spd_decode_spd_size_ddr2(u8 byte0);
 161 u32 spd_decode_eeprom_size_ddr2(u8 byte1);
 162 int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);
 163 void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm);
 164 void normalize_tck(u32 *tclk);
 165 u8 spd_get_msbs(u8 c);
 166 u16 spd_ddr2_calc_unique_crc(const u8 *spd, int len);
 167
 168 #endif /* DEVICE_DRAM_DDR2L_H */