src/include/device/dram/ddr5.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef DEVICE_DRAM_DDR5_H
   4 #define DEVICE_DRAM_DDR5_H
   5
   6 /**
   7  * @file ddr5.h
   8  *
   9  * \brief Utilities for decoding (LP)DDR5 info
  10  */
  11
  12 #include <device/dram/common.h>
  13 #include <types.h>
  14
  15 /** Maximum SPD size supported */
  16 #define SPD_SIZE_MAX_DDR5       1024
  17
  18 enum spd_dimm_type_ddr5 {
  19         SPD_DDR5_DIMM_TYPE_RDIMM = 0x01,
  20         SPD_DDR5_DIMM_TYPE_UDIMM = 0x02,
  21         SPD_DDR5_DIMM_TYPE_SODIMM = 0x03,
  22         SPD_DDR5_DIMM_TYPE_LRDIMM = 0x04,
  23         SPD_DDR5_DIMM_TYPE_MINI_RDIMM = 0x05,
  24         SPD_DDR5_DIMM_TYPE_MINI_UDIMM = 0x06,
  25         SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM = 0x08,
  26         SPD_DDR5_DIMM_TYPE_72B_SO_RDIMM = 0x09,
  27         SPD_DDR5_DIMM_TYPE_SOLDERED_DOWN = 0x0b,
  28         SPD_DDR5_DIMM_TYPE_16B_SO_DIMM = 0x0c,
  29         SPD_DDR5_DIMM_TYPE_32B_SO_RDIMM = 0x0d,
  30         SPD_DDR5_DIMM_TYPE_1DPC = 0x0e,
  31         SPD_DDR5_DIMM_TYPE_2DPC = 0x0f,
  32 };
  33
  34 /**
  35  * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s
  36  */
  37 uint16_t ddr5_speed_mhz_to_reported_mts(uint16_t speed_mhz);
  38
  39 #endif /* DEVICE_DRAM_DDR5_H */