soc/intel/common: Add PCIe device IDs for Snow Ridge
[coreboot2.git] / src / include / device / dram / rcd.h
blobd8429b39b4e475672913fa7adfe3d88b51cdd926
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #ifndef DEVICE_DRAM_RCD_H
4 #define DEVICE_DRAM_RCD_H
6 #include <types.h>
7 #include <device/i2c_simple.h>
9 enum rcw_idx {
10 VEN_ID_L,
11 VEN_ID_H,
12 DEV_ID_L,
13 DEV_ID_H,
14 REV_ID,
15 RES_05,
16 RES_06,
17 RES_07,
18 F0RC00_01,
19 F0RC02_03,
20 F0RC04_05,
21 F0RC06_07,
22 F0RC08_09,
23 F0RC0A_0B,
24 F0RC0C_0D,
25 F0RC0E_0F,
26 F0RC1x,
27 F0RC2x,
28 F0RC3x,
29 F0RC4x,
30 F0RC5x,
31 F0RC6x,
32 F0RC7x,
33 F0RC8x,
34 F0RC9x,
35 F0RCAx,
36 F0RCBx,
37 F0RCCx,
38 F0RCDx,
39 F0RCEx,
40 F0RCFx,
41 RCW_ALL, /* Total num of bytes */
42 RCW_ALL_ALIGNED /* Total num of bytes after aligning to 4B */
45 _Static_assert(RCW_ALL_ALIGNED % sizeof(uint32_t) == 0,
46 "RCW_ALL_ALIGNED is not aligned");
48 /* Write an 8-bit register. Returns the number of written bytes. */
49 int rcd_write_reg(unsigned int bus, uint8_t slave, enum rcw_idx reg,
50 uint8_t data);
52 /* Write 32 bits of memory (i.e., four 8-bit registers, not 1 32-bit register, which would
53 * involve byte swapping). Returns the number of written bytes. */
54 int rcd_write_32b(unsigned int bus, uint8_t slave, enum rcw_idx reg,
55 uint32_t data);
57 /* Dump 32 bytes of RCD onto the screen. */
58 void dump_rcd(unsigned int bus, uint8_t addr);
60 #endif /* DEVICE_DRAM_RCD_H */