soc/intel/common: Add PCIe device IDs for Snow Ridge
[coreboot2.git] / src / include / device / pciexp.h
blob2618c02f321c7148c623c5961523c6ad717f716a
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef DEVICE_PCIEXP_H
4 #define DEVICE_PCIEXP_H
5 /* (c) 2005 Linux Networx GPL see COPYING for details */
6 #include <device/pci_def.h>
8 enum aspm_type {
9 PCIE_ASPM_NONE = 0,
10 PCIE_ASPM_L0S = 1,
11 PCIE_ASPM_L1 = 2,
12 PCIE_ASPM_BOTH = 3,
15 #define ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET 16
16 #define ASPM_LTR_L12_THRESHOLD_VALUE_MASK (0x3ff << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET)
17 #define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29
18 #define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)
20 /* Latency tolerance reporting, max non-snoop latency value 3.14ms */
21 #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003
22 /* Latency tolerance reporting, max snoop latency value 3.14ms */
23 #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003
25 void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
26 unsigned int max_devfn);
28 void pciexp_scan_bridge(struct device *dev);
30 extern struct device_operations default_pciexp_ops_bus;
32 void pciexp_hotplug_scan_bridge(struct device *dev);
34 extern struct device_operations default_pciexp_hotplug_ops_bus;
36 unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap,
37 unsigned int offset);
38 unsigned int pciexp_find_ext_vendor_cap(const struct device *dev, unsigned int cap,
39 unsigned int offset);
41 static inline bool pciexp_is_downstream_port(int type)
43 return type == PCI_EXP_TYPE_ROOT_PORT ||
44 type == PCI_EXP_TYPE_DOWNSTREAM ||
45 type == PCI_EXP_TYPE_PCIE_BRIDGE;
48 bool pciexp_dev_is_slot_hot_plug_cap(struct device *dev);
50 struct device *pcie_find_dsn(const uint64_t serial, const uint16_t vid,
51 struct device *from);
53 bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop);
55 #endif /* DEVICE_PCIEXP_H */