1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <amdblocks/acpi.h>
4 #include <amdblocks/amd_pci_util.h>
5 #include <commonlib/helpers.h>
6 #include <device/device.h>
10 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
11 accessed via I/O ports 0xc00/0xc01. */
14 * This controls the device -> IRQ routing.
17 * 0: timer < soc/amd/common/acpi/lpc.asl
20 * 8: rtc0 <- soc/amd/common/acpi/lpc.asl
21 * 9: acpi <- soc/amd/common/acpi/lpc.asl
23 static const struct fch_irq_routing fch_irq_map
[] = {
24 { PIRQ_A
, 12, PIRQ_NC
},
25 { PIRQ_B
, 14, PIRQ_NC
},
26 { PIRQ_C
, 15, PIRQ_NC
},
27 { PIRQ_D
, 12, PIRQ_NC
},
28 { PIRQ_E
, 14, PIRQ_NC
},
29 { PIRQ_F
, 15, PIRQ_NC
},
30 { PIRQ_G
, 12, PIRQ_NC
},
31 { PIRQ_H
, 14, PIRQ_NC
},
33 { PIRQ_SCI
, ACPI_SCI_IRQ
, ACPI_SCI_IRQ
},
34 { PIRQ_SD
, PIRQ_NC
, PIRQ_NC
},
35 { PIRQ_SDIO
, PIRQ_NC
, PIRQ_NC
},
36 { PIRQ_GPIO
, 11, 11 },
37 { PIRQ_I2C0
, 10, 10 },
44 /* The MISC registers are not interrupt numbers */
45 { PIRQ_MISC
, 0xfa, 0x00 },
46 { PIRQ_MISC0
, 0x91, 0x00 },
47 { PIRQ_HPET_L
, 0x00, 0x00 },
48 { PIRQ_HPET_H
, 0x00, 0x00 },
51 const struct fch_irq_routing
*mb_get_fch_irq_mapping(size_t *length
)
53 *length
= ARRAY_SIZE(fch_irq_map
);
57 static void mainboard_init(void *chip_info
)
59 mainboard_program_gpios();
62 struct chip_operations mainboard_ops
= {
63 .init
= mainboard_init
,