cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / amd / chausie / port_descriptors.c
blob4d7aa8a6c015e313b41c9db258683659a354b642
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <device/i2c_simple.h>
5 #include <gpio.h>
6 #include <soc/platform_descriptors.h>
7 #include <types.h>
9 static const fsp_dxio_descriptor chausie_dxio_descriptors[] = {
10 { /* GBE*/
11 .engine_type = PCIE_ENGINE,
12 .port_present = true,
13 .start_logical_lane = 0,
14 .end_logical_lane = 0,
15 .device_number = 2,
16 .function_number = 1,
17 .link_speed_capability = GEN3,
18 .turn_off_unused_lanes = true,
19 .link_aspm = 2,
20 .link_hotplug = HOTPLUG_ENHANCED,
21 .clk_req = CLK_REQ3,
23 { /* WIFI */
24 .engine_type = PCIE_ENGINE,
25 .port_present = true,
26 .start_logical_lane = 1,
27 .end_logical_lane = 1,
28 .device_number = 2,
29 .function_number = 2,
30 .link_speed_capability = GEN3,
31 .turn_off_unused_lanes = true,
32 .link_aspm = 2,
33 .link_hotplug = HOTPLUG_ENHANCED,
34 .clk_req = CLK_REQ1,
36 { /* NVMe SSD */
37 .engine_type = PCIE_ENGINE,
38 .port_present = true,
39 .start_logical_lane = 2,
40 .end_logical_lane = 3,
41 .device_number = 2,
42 .function_number = 3,
43 .link_speed_capability = GEN3,
44 .turn_off_unused_lanes = true,
45 .link_aspm = 2,
46 .link_hotplug = HOTPLUG_ENHANCED,
47 .gpio_group_id = GPIO_27,
48 .clk_req = CLK_REQ0,
52 static fsp_ddi_descriptor chausie_ddi_descriptors[] = {
53 { /* DDI0 - eDP */
54 .connector_type = DDI_EDP,
55 .aux_index = DDI_AUX1,
56 .hdp_index = DDI_HDP1
58 { /* DDI1 - HDMI/DP */
59 .connector_type = DDI_HDMI,
60 .aux_index = DDI_AUX2,
61 .hdp_index = DDI_HDP2
63 { /* DDI2 - DP (type C) */
64 .connector_type = DDI_DP_W_TYPEC,
65 .aux_index = DDI_AUX3,
66 .hdp_index = DDI_HDP3,
68 { /* DDI3 - DP (type C) */
69 .connector_type = DDI_DP_W_TYPEC,
70 .aux_index = DDI_AUX4,
71 .hdp_index = DDI_HDP4,
73 { /* DDI4 - unused */
74 .connector_type = DDI_UNUSED_TYPE,
75 .aux_index = DDI_AUX5,
76 .hdp_index = DDI_HDP5,
80 static uint8_t get_ddi1_type(void)
82 const uint8_t eeprom_i2c_bus = 2;
83 const uint8_t eeprom_i2c_address = 0x55;
84 const uint16_t eeprom_connector_type_offset = 2;
85 uint8_t eeprom_connector_type_data[2];
86 uint16_t connector_type;
88 if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address,
89 eeprom_connector_type_offset, eeprom_connector_type_data,
90 sizeof(eeprom_connector_type_data))) {
91 printk(BIOS_NOTICE,
92 "Display connector type couldn't be determined. Disabling DDI1.\n");
93 return DDI_UNUSED_TYPE;
96 connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8;
98 switch (connector_type) {
99 case 0xc:
100 printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n");
101 return DDI_HDMI;
102 case 0x13:
103 printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n");
104 return DDI_DP;
105 case 0x14:
106 printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n");
107 return DDI_EDP;
108 default:
109 printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n",
110 connector_type);
111 return DDI_UNUSED_TYPE;
115 void mainboard_get_dxio_ddi_descriptors(
116 const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
117 const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
119 chausie_ddi_descriptors[1].connector_type = get_ddi1_type();
121 *dxio_descs = chausie_dxio_descriptors;
122 *dxio_num = ARRAY_SIZE(chausie_dxio_descriptors);
123 *ddi_descs = chausie_ddi_descriptors;
124 *ddi_num = ARRAY_SIZE(chausie_ddi_descriptors);