src/mainboard/amd/gardenia/bootblock/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/agesawrapper.h>
   4
   5 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
   6
   7 /* Port descriptor list for Gardenia Rev. B */
   8 static const PCIe_PORT_DESCRIPTOR PortList[] = {
   9         /* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
  10         {
  11                 0,
  12                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
  13                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
  14                                 2, 1,
  15                                 HotplugDisabled,
  16                                 PcieGenMaxSupported,
  17                                 PcieGenMaxSupported,
  18                                 AspmL0sL1, 0x04, 0)
  19         },
  20         /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
  21         {
  22                 0,
  23                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),
  24                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
  25                                 2, 2,
  26                                 HotplugDisabled,
  27                                 PcieGenMaxSupported,
  28                                 PcieGenMaxSupported,
  29                                 AspmL0sL1, 0x17, 0)
  30         },
  31         /* Disable M.2 x1 on lane 1, D2F3 */
  32         {
  33                 0,
  34                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
  35                 PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
  36                                 2, 3,
  37                                 HotplugDisabled,
  38                                 PcieGenMaxSupported,
  39                                 PcieGenMaxSupported,
  40                                 AspmL0sL1, 0x17, 0)
  41         },
  42         /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
  43         {
  44                 0,
  45                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
  46                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
  47                                 2, 4,
  48                                 HotplugDisabled,
  49                                 PcieGenMaxSupported,
  50                                 PcieGenMaxSupported,
  51                                 AspmL0sL1, 0x13, 0)
  52         },
  53         /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
  54         {
  55                 DESCRIPTOR_TERMINATE_LIST,
  56                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
  57                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
  58                                 2, 5,
  59                                 HotplugDisabled,
  60                                 PcieGenMaxSupported,
  61                                 PcieGenMaxSupported,
  62                                 AspmL0sL1, 0x16, 0)
  63         },
  64 };
  65
  66 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
  67         /* DDI0 - eDP */
  68         {
  69                 0,
  70                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
  71                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
  72         },
  73         /* DDI1 - DP */
  74         {
  75                 0,
  76                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
  77                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
  78         },
  79         /* DDI2 - HDMI */
  80         {
  81                 DESCRIPTOR_TERMINATE_LIST,
  82                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
  83                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
  84         },
  85 };
  86
  87 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  88         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  89         .SocketId     = 0,
  90         .PciePortList = (void *)PortList,
  91         .DdiLinkList  = (void *)DdiList
  92 };
  93
  94 static const UINT32 AzaliaCodecAlc286Table[] = {
  95         0x00172051, 0x001721C7, 0x00172222, 0x00172310,
  96         0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
  97         0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
  98         0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,
  99         0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,
 100         0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,
 101         0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,
 102         0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,
 103         0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,
 104         0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,
 105         0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,
 106         0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,
 107         0x02050071, 0x02040014, 0x02050010, 0x02040C22,
 108         0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,
 109         0x0205002D, 0x02041020, 0x02050020, 0x02040000,
 110         0x02050019, 0x02040817, 0x02050035, 0x02041AA5,
 111         0x02050063, 0x02042906, 0x02050063, 0x02042906,
 112         0xffffffff
 113 };
 114
 115 static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
 116         { 0x10ec0286, AzaliaCodecAlc286Table},
 117         { 0x0FFFFFFFF, (void *)0x0FFFFFFFF}
 118 };
 119
 120 /*---------------------------------------------------------------------------*/
 121 /**
 122  *  OemCustomizeInitEarly
 123  *
 124  *  Description:
 125  *    This is the stub function will call the host environment through the
 126  *    binary block interface (call-out port) to provide a user hook opportunity.
 127  *
 128  *  Parameters:
 129  *    @param[in]      **PeiServices
 130  *    @param[in]      *InitEarly
 131  *
 132  *    @retval         VOID
 133  *
 134  **/
 135 /*---------------------------------------------------------------------------*/
 136 VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 137 {
 138         InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
 139         InitEarly->PlatformConfig.AzaliaCodecVerbTable =
 140                                         (uint64_t)(uintptr_t)CodecTableList;
 141 }